Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 286  2010 Microchip Technology Inc.
REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 U-0 U-0 U-0 U-0 R/P-0 U-0 R/P-1
MCLRE
— — — — LPT1OSC — CCP2MX
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MCLRE: MCLR Pin Enable bit
1 = MCLR
pin is enabled; RG5 input pin is disabled
0 = RG5 input pin is enabled; MCLR
is disabled
bit 6-3 Unimplemented: Read as ‘0’
bit 2 LPT1OSC: Low-Power Timer 1 Oscillator Enable bit
1 = Timer1 is configured for low-power operation
0 = Timer1 is configured for higher power operation
bit 1 Unimplemented: Read as ‘0
bit 0 CCP2MX: CCP2 MUX bit
In Microcontroller Mode only (all devices):
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RE7
In Microprocessor, Extended Microcontroller and Microcontroller with Boot Block Modes
(PIC18F8310/8410 devices only):
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3