Datasheet

 2010 Microchip Technology Inc. DS39635C-page 263
PIC18F6310/6410/8310/8410
20.6 A/D Conversions
Figure 20-4 shows the operation of the A/D Converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into Sleep mode before the
conversion begins.
Figure 20-5 shows the operation of the A/D Converter
after the GO/DONE
bit has been set and the
ACQT<2:0> bits are set to ‘010’, and selecting a 4 T
AD
acquisition time before the conversion starts.
Clearing the GO/DONE
bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
20.7 Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge the capacitor array, rather than
charge/discharge based on previous measure values.
FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 20-5: A/D CONVERSION T
AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2
TAD3
TAD4 TAD5
TAD6 TAD7
TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle:
TAD1
Discharge
1
2
3 4 5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Conversion starts
1
2
3 4
(Holding capacitor continues
acquiring input)
T
ACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0b9
b6
b5 b4
b3
b2
b1
b8
b7
ADRESH:ADRESL are loaded, GO/DONE
bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
TAD1
Discharge