Datasheet

 2010 Microchip Technology Inc. DS39635C-page 241
PIC18F6310/6410/8310/8410
19.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module,
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices, for those situations that do not require
Auto-Baud Detection (ABD) or LIN/J2602 bus support.
The AUSART can be configured in the following
modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2, respectively). In order to configure
these pins as an AUSART:
• SPEN bit (RCSTA2<7>) must be set (= 1)
• TRISG<2> bit must be set (= 1)
• TRISG<1> bit must be cleared (= 0) for
Asynchronous and Synchronous Master modes
• TRISG<1> bit must be set (= 1) for Synchronous
Slave mode
The operation of the Addressable USART module is
controlled through two registers: TXSTA2 and
RXSTA2. These are detailed in Register 19-1 and
Register 19-2 respectively.
Note: The USART control will automatically
reconfigure the pin from input to output as
needed.