Datasheet

 2010 Microchip Technology Inc. DS39635C-page 221
PIC18F6310/6410/8310/8410
18.1 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the period
of a free running timer. In Asynchronous mode, bits,
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>),
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 18-1 shows the formula for computation
of the baud rate for different EUSART modes that only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
OSC, the nearest
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 18-1. From
this, the error in baud rate can be determined. An
example calculation is shown in Example 18-1. Typical
baud rates and error values for the various
Asynchronous modes are shown in Table 18-2. It may
be advantageous to use the high baud rate (BRGH = 1)
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer
overflow before outputting the new baud rate.
18.1.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
18.1.2 SAMPLING
The data on the RXx pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RXx pin when SYNC is clear or
when both BRG16 and BRGH are not set. The data on
the RXx pin is sampled once when SYNC is set or
when BRGH16 and BRGH are both set.
TABLE 18-1: BAUD RATE FORMULAS
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
TABLE 18-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Note: The BRG value of ‘0’ is not supported.
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n + 1)]
001 8-bit/Asynchronous
FOSC/[16 (n + 1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
F
OSC/[4 (n + 1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page
TXSTA1
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))
Solving for SPBRGH1:SPBRG1:
X = ((F
OSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%