Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 172  2010 Microchip Technology Inc.
TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63
RCON IPEN
SBOREN — RI TO PD POR BOR 64
PIR1
PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65
PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65
IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65
PIR2
OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65
PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65
IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65
PIR3
— — RC2IF TX2IF — — — CCP3IF 65
PIE3 — — RC2IE TX2IE — — — CCP3IE 65
IPR3 — — RC2IP TX2IP — — — CCP3IP 65
TRISB PORTB Data Direction Register 66
TRISC PORTC Data Direction Register 66
TRISE PORTE Data Direction Register 66
TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register 64
TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register 64
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 64
TMR3H Timer3 Register High Byte 65
TMR3L Timer3 Register Low Byte 65
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 65
CCPR1L Capture/Compare/PWM Register 1 (LSB) 65
CCPR1H Capture/Compare/PWM Register 1 (MSB) 65
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 65
CCPR2L Capture/Compare/PWM Register 2 (LSB) 65
CCPR2H Capture/Compare/PWM Register 2 (MSB) 65
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 65
CCPR3L Capture/Compare/PWM Register 3 (LSB) 65
CCPR3H Capture/Compare/PWM Register 3 (MSB) 65
CCP3CON
— — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.