Datasheet

 2010 Microchip Technology Inc. DS39635C-page 143
PIC18F6310/6410/8310/8410
TABLE 11-13: PORTG FUNCTIONS
TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/CCP3 RG0 0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
CCP3 0 O DIG CCP3 compare and PWM output; takes priority over port data.
1 I ST CCP3 capture input.
RG1/TX2/CK2 R21 0 O DIG LATG<1> data output.
1 I ST PORTG<1> data input.
TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
CK2 1 O DIG Synchronous serial data input (AUSART module). User must
configure as an input.
1 I ST Synchronous serial clock input (AUSART module).
RG2/RX2/DT2 RG2 0 O DIG LATG<2> data output.
1 I ST PORTG<2> data input.
RX2 1 I ST Asynchronous serial receive data input (AUSART module).
DT2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (AUSART module). User must
configure as an input.
RG3 RG3 0 O DIG LATG<3> data output.
1 I ST PORTG<3> data input.
RG4 RG4 0 O DIG LATG<4> data output.
1 I ST PORTG<4> data input.
RG5/MCLR
/VPP RG5 —
(1)
I ST PORTG<5> data input; enabled when MCLRE Configuration bit is
clear.
MCLR
— I ST External Master Clear input; enabled when MCLRE Configuration bit is
set.
V
PP — I ANA High-Voltage Detection; used for ICSP™ mode entry detection.
Always available, regardless of pin mode.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RG5 does not have a corresponding TRISG bit.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
PORTG
— —RG5
(1)
RG4 RG3 RG2 RG1 RG0 66
LATG
— — — LATG Output Latch Register 66
TRISG — — — PORTG Data Direction Register 66
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: RG5 is available as an input only when MCLR is disabled.