Datasheet

 2010 Microchip Technology Inc. DS39635C-page 103
PIC18F6310/6410/8310/8410
8.3.1 8-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 8-4 through Figure 8-6.
FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
FIGURE 8-9: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q4Q4 Q4 Q4
ALE
OE
ABh
WRL
AD<7:0>
BA0
33h
Opcode Fetch
MOVLW 55h
from 007556h
92h
55h
‘1’
‘1’
Table Read
of 92h
from 199E67h
1 T
CY Wait
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Apparent Q
Actual Q
A<19:16>
0Ch
00h
CE
‘0’
‘0’
Memory
Cycle
Instruction
Execution
TBLRD Cycle 1
TBLRD Cycle 2
3Ah
AD<15:8> CFh
0Eh
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Q2Q1 Q3 Q4
A<19:16>
ALE
OE
AD<7:0>
CE
Opcode Fetch Opcode Fetch Opcode Fetch
TBLRD *
TBLRD Cycle 1
ADDLW 55h
from 000100h
Q2Q1 Q3 Q4
0Ch
33h
TBLRD 92h
from 199E67h
92h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 2
MOVLW 55h
from 000102h
MOVLW
AD<15:8>
CFh