Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (10x10) 8-Bit 40 MHz I/O number 54

 2010 Microchip Technology Inc. DS39635C

PIC18F6310/6410/8310/8410

Data Sheet

64/80-Pin Flash Microcontrollers

with nanoWatt XLP Technology

Summary of content (412 pages)

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PIC18F6310/6410/8310/8410 Data Sheet 64/80-Pin Flash Microcontrollers with nanoWatt XLP Technology  2010 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers with nanoWatt Technology Power-Managed Modes: Peripheral Highlights (Continued): • • • • • • • • • • • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes • Addressable USART module: - Supports RS-485 and RS-232 • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-Wake-up on Start bit - Auto-Baud Detect • 10-Bit, up to 12-Channel Analog-to-Digital (A/D) Co
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PIC18F6310/6410/8310/8410 Pin Diagrams RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RD0/PSP0 RE7/CCP2(1) RE6 RE5 RE4 RE3 RE2/CS 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR RE0/RD RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG5/MCLR/VPP RG4 VSS VDD RF7/SS RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 47 46 45 44 43 42 41 40 PIC18F6310 PIC18F6410 39 38 37 36 35 34 33 15 16 RB0/INT0 RB1/INT1 RB2/INT2
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PIC18F6310/6410/8310/8410 Pin Diagrams (Continued) RJ1/OE RJ0/ALE RD7/AD7/PSP7 RD6/AD6/PSP6 RD5/AD5/PSP5 RD4/AD4/PSP4 RD3/AD3/PSP3 RD2/AD2/PSP2 RD1/AD1/PSP1 VSS VDD RE7/CCP2(1)/AD15 RD0/AD0/PSP0 RE6/AD14 RE5/AD13 RE4/AD12 RE3/AD11 RH0/A16 RE2/AD10/CS RH1/A17 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 RE1/AD9/WR RE0/AD8/RD RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG5/MCLR/VPP RG4 VSS VDD RF7/SS RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT
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PIC18F6310/6410/8310/8410 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 31 3.0 Oscillator Configurations ............................................................................
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PIC18F6310/6410/8310/8410 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 8  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6310 • PIC18LF6310 • PIC18F6410 • PIC18LF6410 • PIC18F8310 • PIC18LF8310 • PIC18F8410 • PIC18LF8410 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price.
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PIC18F6310/6410/8310/8410 1.2 Other Special Features • Memory Endurance: The Flash cells for program memory are rated to last for approximately a thousand erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 100 years. • External Memory Interface: For those applications where more program or data storage is needed, the PIC18F8310/8410 devices provide the ability to access external memory devices.
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PIC18F6310/6410/8310/8410 TABLE 1-1: DEVICE FEATURES Features PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410 DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz 8K 16K 8K 16K Program Memory (Instructions) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 External Memory Interface No No Yes Yes Interrupt Sources 22 22 22 22 Operating Frequency Program Memory (Bytes) I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G,
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PIC18F6310/6410/8310/8410 FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM PORTA Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory (8/16 Kbytes) PCLATU PCLATH 21 20 Address Latch PCU PCH PCL Program Counter 31 Level Stack Program Memory 8/16 Kbytes) 4 BSR STKPTR RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 Data Address<12> Address Latch 12 inc/dec logic Table Latch PORTC
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PIC18F6310/6410/8310/8410 FIGURE 1-2: PIC18F8310/8410 (80-PIN) BLOCK DIAGRAM PORTA Data Bus<8> Table Pointer<21> 8 inc/dec logic 21 Data Latch 8 Data Memory (8/16 Kbytes) PCLATU PCLATH 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 System Bus Interface Address Latch Program Memory (8/16 Kbytes) PORTB 4 12 BSR STKPTR Access Bank FSR0 FSR1 FSR2 Data Latch TABLE LATCH RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR/VPP RG5 MCLR I I ST ST P 39 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 7 VPP OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 27 I/O I TTL Analog Digital I/O. Analog Input 0. I/O I TTL Analog Digital I/O. Analog Input 1. I/O I I TTL Analog Analog Digital I/O. Analog Input 2.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 48 RB1/INT1 RB1 INT1 47 RB2/INT2 RB2 INT2 46 RB3/INT3 RB3 INT3 45 RB4/KBI0 RB4 KBI0 44 RB5/KBI1 RB5 KBI1 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 I/O I TTL ST Digital I/O. External Interrupt 0.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(1) 29 RC2/CCP1 RC2 CCP1 33 RC3/SCK/SCL RC3 SCK SCL 34 RC4/SDI/SDA RC4 SDI SDA 35 RC5/SDO RC5 SDO 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O O I ST — ST I/O I I/O ST Analog ST Digital I/O. Timer1 oscillator input.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/PSP0 RD0 PSP0 58 RD1/PSP1 RD1 PSP1 55 RD2/PSP2 RD2 PSP2 54 RD3/PSP3 RD3 PSP3 53 RD4/PSP4 RD4 PSP4 52 RD5/PSP5 RD5 PSP5 51 RD6/PSP6 RD6 PSP6 50 RD7/PSP7 RD7 PSP7 49 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O ST TTL Digital I/O. Parallel Slave Port data.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/RD RE0 RD 2 RE1/WR RE1 WR 1 RE2/CS RE2 CS 64 RE3 I/O I ST TTL Digital I/O. Read control for Parallel Slave Port. I/O I ST TTL Digital I/O. Write control for Parallel Slave Port. I/O I ST TTL Digital I/O. Chip select control for Parallel Slave Port. 63 I/O ST Digital I/O.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS RF7 SS 11 I/O I ST Analog Digital I/O. Analog Input 5. I/O I O ST Analog — Digital I/O. Analog Input 6.
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PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/CCP3 RG0 CCP3 3 RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3 RG4 I/O I/O ST ST Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. I/O O I/O ST — ST Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). I/O I I/O ST ST ST Digital I/O.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR/VPP RG5 MCLR I I ST ST P 49 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 9 VPP OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI RA4 T0CKI 34 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 33 I/O I TTL Analog Digital I/O. Analog Input 0. I/O I TTL Analog Digital I/O. Analog Input 1. I/O I I TTL Analog Analog Digital I/O. Analog Input 2.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 58 RB1/INT1 RB1 INT1 57 RB2/INT2 RB2 INT2 56 RB3/INT3/CCP2 RB3 INT3 CCP2(1) 55 RB4/KBI0 RB4 KBI0 54 RB5/KBI1 RB5 KBI1 53 RB6/KBI2/PGC RB6 KBI2 PGC 52 RB7/KBI3/PGD RB7 KBI3 PGD 47 I/O I TTL ST Digital I/O.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 35 RC2/CCP1 RC2 CCP1 43 RC3/SCK/SCL RC3 SCK SCL 44 RC4/SDI/SDA RC4 SDI SDA 45 RC5/SDO RC5 SDO 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 I/O O I ST — ST Digital I/O. Timer1 oscillator output.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/AD0/PSP0 RD0 AD0 PSP0 72 RD1/AD1/PSP1 RD1 AD1 PSP1 69 RD2/AD2/PSP2 RD2 AD2 PSP2 68 RD3/AD3/PSP3 RD3 AD3 PSP3 67 RD4/AD4/PSP4 RD4 AD4 PSP4 66 RD5/AD5/PSP5 RD5 AD5 PSP5 65 RD6/AD6/PSP6 RD6 AD6 PSP6 64 RD7/AD7/PSP7 RD7 AD7 PSP7 63 I/O I/O I/O ST TTL TTL Digital I/O. External Memory Address/Data 0.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AD8/RD RE0 AD8 RD 4 RE1/AD9/WR RE1 AD9 WR 3 RE2/AD10/CS RE2 AD10 CS 78 RE3/AD11 RE3 AD11 77 RE4/AD12 RE4 AD12 76 RE5/AD13 RE5 AD13 75 RE6/AD14 RE6 AD14 74 RE7/CCP2/AD15 RE7 CCP2(3) AD15 73 I/O I/O I ST TTL TTL Digital I/O. External Memory Address/Data 8. Read control for Parallel Slave Port.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 24 RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS RF7 SS 13 I/O I ST Analog Digital I/O. Analog Input 5. I/O I O ST Analog — Digital I/O. Analog Input 6.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/CCP3 RG0 CCP3 5 RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2 RG2 RX2 DT2 7 RG3 RG4 I/O I/O ST ST Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. I/O O I/O ST — ST Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). I/O I I/O ST ST ST Digital I/O.
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PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ4 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 VSS 11, 31, 51, 70 I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable.
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PIC18F6310/6410/8310/8410 2.
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PIC18F6310/6410/8310/8410 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
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PIC18F6310/6410/8310/8410 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1.
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PIC18F6310/6410/8310/8410 2.5 External Oscillator Pins FIGURE 2-3: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
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PIC18F6310/6410/8310/8410 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types FIGURE 3-1: PIC18F6310/6410/8310/8410 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6.
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PIC18F6310/6410/8310/8410 TABLE 3-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
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PIC18F6310/6410/8310/8410 3.4 RC Oscillator 3.5 For timing-insensitive applications, the “RC” and “RCIO” device options offer additional cost savings.
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PIC18F6310/6410/8310/8410 3.6 Internal Oscillator Block The PIC18F6310/6410/8310/8410 devices include an internal oscillator block, which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock.
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PIC18F6310/6410/8310/8410 3.6.5.1 Compensating with the AUSART An adjustment may be required when the AUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSTUNE to increase the clock frequency. 3.6.5.
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PIC18F6310/6410/8310/8410 The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F6310/6410/8310/8410 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source.
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PIC18F6310/6410/8310/8410 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<3:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
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PIC18F6310/6410/8310/8410 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Intern
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PIC18F6310/6410/8310/8410 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 44  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 4.0 4.1.1 POWER-MANAGED MODES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F6310/6410/8310/8410 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
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PIC18F6310/6410/8310/8410 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
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PIC18F6310/6410/8310/8410 On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). FIGURE 4-1: When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock.
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PIC18F6310/6410/8310/8410 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive, or do not require high-speed clocks at all times.
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PIC18F6310/6410/8310/8410 FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 INTRC 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 4-4: PC + 2 PC + 4 TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS<1:0> bits Changed PC + 4 OSTS bit S
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PIC18F6310/6410/8310/8410 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F6310/6410/8310/8410 devices is identical to the legacy Sleep mode offered in all other PIC® devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (see Figure 4-5). All clock source status bits are cleared.
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PIC18F6310/6410/8310/8410 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. When a wake event occurs, the CPU is clocked from the primary clock source.
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PIC18F6310/6410/8310/8410 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS<1:0> to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set.
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PIC18F6310/6410/8310/8410 4.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 “Run Modes” through Section 4.4 “Idle Modes”). 4.5.
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PIC18F6310/6410/8310/8410 TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Clock Source After Wake-up Exit Delay LP, XT, HS Primary Device Clock (PRI_IDLE mode) HSPLL EC, RC, INTRC(1) OSTS TCSD (2) — INTOSC(3) T1OSC or INTRC(1) TOST(4) HSPLL TOST + trc(4) EC, RC, INTRC(1) TCSD(2) INTOSC INTOSC(3) 3: 4: 5: — IOFS TOST(5) HSPLL TOST + trc(4) EC, RC, INTRC(1) TCSD(2) — None IOFS INTOSC Note 1: 2: TIOBST (5
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PIC18F6310/6410/8310/8410 5.0 RESET 5.1 The PIC18F6310/6410/8310/8410 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
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PIC18F6310/6410/8310/8410 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0(1) U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR
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PIC18F6310/6410/8310/8410 5.2 Master Clear (MCLR) The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 Extended MCU devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F6310/6410/8310/8410 devices, the MCLR input can be disabled with the MCLRE Configuration bit.
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PIC18F6310/6410/8310/8410 5.4 Brown-out Reset (BOR) PIC18F6310/6410/8310/8410 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR configurations, which are summarized in Table 5-1. The BOR threshold is set by the BORV<1:0> bits.
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PIC18F6310/6410/8310/8410 5.5 5.5.3 Device Reset Timers PIC18F6310/6410/8310/8410 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.
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PIC18F6310/6410/8310/8410 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 5-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39635C-page 60 
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PIC18F6310/6410/8310/8410 FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) FIGURE 5-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer.  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
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PIC18F6310/6410/8310/8410 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 6X10 8X10 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X10 8X10 0000 0000 0000 0000 uuuu uuuu(3) TOSL 6X10 8X10 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 6X10 8X10 uu-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 6X10 8X10 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X10
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PIC18F6310/6410/8310/8410 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt INDF2 6X10 8X10 N/A N/A N/A POSTINC2 6X10 8X10 N/A N/A N/A POSTDEC2 6X10 8X10 N/A N/A N/A PREINC2 6X10 8X10 N/A N/A N/A PLUSW2 6X10 8X10 N/A N/A N/A FSR2H 6X10 8X10 ---- xxxx ---- uuuu ---- uuuu FSR2L 6X10 8X10 xxxx xxxx uuuu uuuu
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PIC18F6310/6410/8310/8410 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt CCPR1H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu CCPR2H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu CCP2CO
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PIC18F6310/6410/8310/8410 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TRISG 6X10 8X10 ---1 1111 ---1 1111 ---u uuuu TRISF 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISE 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISD 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISC 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISB 6X10
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PIC18F6310/6410/8310/8410 6.0 MEMORY ORGANIZATION 6.1 There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Program Memory”.
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PIC18F6310/6410/8310/8410 6.1.1 PIC18F8310/8410 PROGRAM MEMORY MODES In addition to available on-chip Flash program memory, 80-pin devices in this family can also address up to 2 Mbytes of external program memory through an external memory interface.
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PIC18F6310/6410/8310/8410 FIGURE 6-2: MEMORY MAPS FOR PIC18FX310/X410 PROGRAM MEMORY MODES Microcontroller Mode(1) Extended Microcontroller Mode(2) 000000h 000000h On-Chip Program Memory On-Chip Program Memory (Top of Memory) (Top of Memory) + 1 (Top of Memory) (Top of Memory) + 1 Reads ‘0’s External Program Memory 1FFFFFh 1FFFFFh On-Chip Flash External Memory Microprocessor Mode(2) 000000h On-Chip Flash Microprocessor with Boot Block Mode(2) On-Chip Program Memory 000000h 0007FFh 000800h (No
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PIC18F6310/6410/8310/8410 6.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
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PIC18F6310/6410/8310/8410 6.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software, or until a POR occurs. The STKPTR register (Register 6-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit.
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PIC18F6310/6410/8310/8410 6.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
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PIC18F6310/6410/8310/8410 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC18F6310/6410/8310/8410 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 6.1.2 “Program Counter”).
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PIC18F6310/6410/8310/8410 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
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PIC18F6310/6410/8310/8410 FIGURE 6-6: DATA MEMORY MAP FOR PIC18F6310/6410/8310/8410 DEVICES BSR<3:0> 00h = 0000 = 0001 = 0010 Bank 0 FFh 00h GPR 000h 05Fh 060h 0FFh 100h GPR Bank 1 Bank 2 Access RAM 1FFh 200h FFh 00h The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15).
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PIC18F6310/6410/8310/8410 FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 1 0 000h Data Memory Bank 0 100h Bank 1 Bank Select(2) 200h 300h Bank 2 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.
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PIC18F6310/6410/8310/8410 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-2 and Table 6-3.
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PIC18F6310/6410/8310/8410 TABLE 6-3: File Name REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 63, 70 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 63, 70 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 63, 70 TOSU STKPTR PCLATU Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR STKFUL(6) STKUNF(6) — Return Stack Pointer 00-0 0000 63, 71 — — — Holding Register for PC<20:16> ---0 00
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PIC18F6310/6410/8310/8410 TABLE 6-3: File Name REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TMR0H Timer0 Register High Byte 0000 0000 64, 153 TMR0L Timer0 Register Low Byte xxxx xxxx 64, 153 64, 151 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 42, 64 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3
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PIC18F6310/6410/8310/8410 TABLE 6-3: File Name REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: SPBRG1 EUSART1 Baud Rate Generator Low Byte 0000 0000 65, 221 RCREG1 EUSART1 Receive Register 0000 0000 65, 229 TXREG1 EUSART1 Transmit Register xxxx xxxx 65, 226 65, 218 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 000
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PIC18F6310/6410/8310/8410 TABLE 6-3: File Name SPBRGH1 BAUDCON1 REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 66, 221 TXCKP BRG16 — WUE ABDEN 0100 0-00 66, 220 EUSART1 Baud Rate Generator High Byte ABDOVF RCIDL RXDTP Details on page: SPBRG2 AUSART2 Baud Rate Generator 0000 0000 66, 234 RCREG2 AUSART2 Receive Register 0000 0000 66, 248 TXREG2 AUSART2 Transmit Register xxxx xxxx 66, 246
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PIC18F6310/6410/8310/8410 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-3, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
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PIC18F6310/6410/8310/8410 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
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PIC18F6310/6410/8310/8410 6.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
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PIC18F6310/6410/8310/8410 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.4.3.
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PIC18F6310/6410/8310/8410 FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f  60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
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PIC18F6310/6410/8310/8410 6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
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PIC18F6310/6410/8310/8410 7.0 PROGRAM MEMORY For PIC18FX310/X410 devices, the on-chip program memory is implemented as read-only memory. It is readable over the entire VDD range during normal operation; it cannot be written to or erased. Reads from program memory are executed one byte at a time. PIC18F8410 devices also implement the ability to read, write to and execute code from external memory devices using the external memory interface.
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PIC18F6310/6410/8310/8410 7.2 Control Registers Two control registers are used in conjunction with the TBLRD and TBLWT instructions: the TABLAT register and the TBLPTR register set. 7.2.1 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between the program memory space and data RAM. 7.2.
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PIC18F6310/6410/8310/8410 FIGURE 7-2: READS FROM PROGRAM MEMORY Program Memory Space (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 7-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVF TABLAT, W WORD_EVEN TABLAT, W WO
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PIC18F6310/6410/8310/8410 7.4 Writing to Program Memory Space (PIC18F8310/8410 only) The table write operation outputs the contents of the TBLPTR and TABLAT registers to the external address and data busses of the external memory interface. Depending on the program memory mode selected, the operation may target any byte address in the device’s memory space. What happens to this data depends largely on the external memory device being used.
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PIC18F6310/6410/8310/8410 TABLE 7-2: Name TBLPTRU REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Bit 7 Bit 6 Bit 5 — — bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Reset Values on Page 63 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 63 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 63 TABLAT Program Memory Table Latch 63 Legend: — = unimplemented, read as ‘0’.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 94  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 8.0 EXTERNAL MEMORY INTERFACE Note: The external memory interface is not implemented on PIC18F6310 and PIC18F6410 (64-pin) devices. The external memory interface allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It is implemented with 28 pins, multiplexed across four I/O ports.
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PIC18F6310/6410/8310/8410 TABLE 8-1: Name PIC18F8310/8410 EXTERNAL BUS – I/O PORT FUNCTIONS Port Bit Function RD0/AD0/PSP0 PORTD 0 Input/Output or System Bus Address bit 0 or Data bit 0 or Parallel Slave Port bit 0 RD1/AD1/PSP1 PORTD 1 Input/Output or System Bus Address bit 1 or Data bit 1 or Parallel Slave Port bit 1 RD2/AD2/PSP2 PORTD 2 Input/Output or System Bus Address bit 2 or Data bit 2 or Parallel Slave Port bit 2 RD3/AD3/PSP3 PORTD 3 Input/Output or System Bus Address bit 3 or Dat
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PIC18F6310/6410/8310/8410 When the device is executing out of internal memory (EBDIS = 0) in Microprocessor with Boot Block mode or Extended Microcontroller mode, the control signals will NOT be active. They will go to a state where the AD<15:0> and A<19:16> are tri-state; the CE, OE, WRH, WRL, UB and LB signals are ‘1’; ALE and BA0 are ‘0’. Note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as I/O.
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PIC18F6310/6410/8310/8410 8.2.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F8410 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
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PIC18F6310/6410/8310/8410 8.2.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
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PIC18F6310/6410/8310/8410 8.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 through Figure 8-6.
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PIC18F6310/6410/8310/8410 FIGURE 8-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q4 Q1 Q2 00h A<19:16> AD<15:0> Q3 3AAAh Q3 Q4 Q1 00h 0003h 3AABh 0E55h CE ALE OE Memory Cycle Instruction Execution Note 1: Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC – 2) SLEEP Sleep Mode, Bus Inactive(1) Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed.  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 8.3 The Address Latch Enable (ALE) pin indicates that the address bits, A<15:0>, are available on the external memory interface bus. The Output Enable signal (OE) will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode.
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PIC18F6310/6410/8310/8410 8.3.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 through Figure 8-6.
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PIC18F6310/6410/8310/8410 FIGURE 8-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 00h A<19:16> AD<15:8> AAh 00h Q4 Q1 00h 3Ah AD<7:0> Q3 3Ah 03h ABh 0Eh 55h CE ALE OE Memory Cycle Instruction Execution Note 1: Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC – 2) SLEEP Sleep Mode, Bus Inactive(1) Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed.
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PIC18F6310/6410/8310/8410 8.4 Operation in Power-Managed Modes In alternate, power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory operations.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 106  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 9-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
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PIC18F6310/6410/8310/8410 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
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PIC18F6310/6410/8310/8410 10.0 INTERRUPTS The PIC18F6310/6410/8310/8410 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the lowpriority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
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PIC18F6310/6410/8310/8410 FIGURE 10-1: PIC18F6310/6410/8310/8410 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> Interrupt to CPU Vector to Location 0008h GIEH/GIE IPE PIR3<5:4, 0> PIE3<5:4, 0> IPR3<5:4, 0> IPEN GIEL/PEIE IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7
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PIC18F6310/6410/8310/8410 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure that the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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PIC18F6310/6410/8310/8410 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: Exte
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PIC18F6310/6410/8310/8410 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority
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PIC18F6310/6410/8310/8410 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
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PIC18F6310/6410/8310/8410 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in softwa
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PIC18F6310/6410/8310/8410 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 — — RC2IF TX21F — — — CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: AUSART Receive Interrupt Flag bit 1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 =
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PIC18F6310/6410/8310/8410 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
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PIC18F6310/6410/8310/8410 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemen
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PIC18F6310/6410/8310/8410 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R-0 R-0 U-0 U-0 U-0 R/W-0 — — RC2IE TX2IE — — — CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: AUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bi
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PIC18F6310/6410/8310/8410 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
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PIC18F6310/6410/8310/8410 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low prio
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PIC18F6310/6410/8310/8410 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R-1 R-1 U-0 U-0 U-0 R/W-1 — — RC2IP TX21P — — — CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: AUSART Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: AUSART Transmit Interrupt Priority bit 1 = High priority
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PIC18F6310/6410/8310/8410 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
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PIC18F6310/6410/8310/8410 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set.
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PIC18F6310/6410/8310/8410 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
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PIC18F6310/6410/8310/8410 TABLE 11-1: Pin Name PORTA FUNCTIONS Function TRIS Setting I/O I/O Type RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled.
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PIC18F6310/6410/8310/8410 TABLE 11-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 66 (1) LATA LATA7 TRISA TRISA7(1) ADCON1 LATA6(1) LATA Output Latch Register TRISA6 — — (1) 66 PORTA Data Direction Register VCFG1 VCFG0 PCFG3 66 PCFG2 PCFG1 PCFG0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
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PIC18F6310/6410/8310/8410 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATB) is also memory mapped.
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PIC18F6310/6410/8310/8410 TABLE 11-3: Pin Name RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/ CCP2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: 2: PORTB FUNCTIONS Function TRIS Setting I/O I/O Type RB0 0 O DIG 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. RB1 0 O DIG LATB<1> data output. Description LATB<0> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
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PIC18F6310/6410/8310/8410 TABLE 11-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 66 LATB LATB Output Latch Register 66 TRISB PORTB Data Direction Register 66 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTCON3 INT2IP TMR0IF INT0IF RBIF 63 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 63 INT2IF INT1IF 63 INT1IP TMR0IE INT3IE INT0IE INT2IE RBIE INT1IE IN
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PIC18F6310/6410/8310/8410 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATC) is also memory mapped.
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PIC18F6310/6410/8310/8410 TABLE 11-5: PORTC FUNCTIONS Pin Name Function RC0/T1OSO/T13CKI RC0 RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC7/RX1/DT1 Legend: Note 1: Description O DIG I ST T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O.
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PIC18F6310/6410/8310/8410 TABLE 11-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 66 LATC LATC Output Latch Register 66 TRISC PORTC Data Direction Register 66  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 11.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATD) is also memory mapped.
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PIC18F6310/6410/8310/8410 TABLE 11-7: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. x O DIG External memory interface, Address/Data Bit 0 output.(1) x I TTL External memory interface, Data Bit 0 input.
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PIC18F6310/6410/8310/8410 TABLE 11-7: PORTD FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RD7/AD7/PSP7 RD7 0 O DIG LATD<7> data output. AD7(2) PSP7 Legend: Note 1: 2: PORTD 1 I ST PORTD<7> data input. x O DIG External memory interface, Address/Data Bit 7 output(1). x I TTL External memory interface, Data Bit 7 input(1). x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input.
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PIC18F6310/6410/8310/8410 11.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATE) is also memory mapped.
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PIC18F6310/6410/8310/8410 TABLE 11-9: Pin Name PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. x O DIG External memory interface, Address/Data Bit 8 output.(2) x I TTL External memory interface, Data Bit 8 input.(2) RD 1 I TTL Parallel Slave Port read enable control input. RE1 0 O DIG LATE<1> data output. 1 I ST PORTE<1> data input. x O DIG External memory interface, Address/Data Bit 9 output.
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PIC18F6310/6410/8310/8410 TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 66 LATE LATE Output Latch Register 66 TRISE PORTE Data Direction Register 66  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 11.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATF) is also memory mapped.
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PIC18F6310/6410/8310/8410 TABLE 11-11: PORTF FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RF0 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input is enabled. RF0/AN5 RF1/AN6/C2OUT AN5 1 I ANA A/D Input Channel 5. Default configuration on POR. RF1 0 O DIG LATF<1> data output; not affected by analog input. 1 I ST 1 I ANA A/D Input Channel 6. Default configuration on POR.
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PIC18F6310/6410/8310/8410 11.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide, bidirectional port. The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). The sixth pin of PORTG (RG5/MCLR/VPP) is an input only pin.
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PIC18F6310/6410/8310/8410 TABLE 11-13: PORTG FUNCTIONS Pin Name RG0/CCP3 Function TRIS Setting I/O I/O Type RG0 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. 0 O DIG CCP3 compare and PWM output; takes priority over port data. 1 I ST CCP3 capture input. 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (AUSART module).
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PIC18F6310/6410/8310/8410 11.8 Note: PORTH, LATH and TRISH Registers PORTH is only available PIC18F8310/8410 devices. on PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin).
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PIC18F6310/6410/8310/8410 TABLE 11-15: PORTH FUNCTIONS Pin Name RH0/AD16 RH1/AD17 RH2/AD18 RH3/AD19 RH4 RH5 RH6 RH7 Legend: Function TRIS Setting I/O I/O Type RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. AD16 x O DIG External memory interface, Address Line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. AD17 x O DIG External memory interface, Address Line 17. Takes priority over port data.
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PIC18F6310/6410/8310/8410 11.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available PIC18F8310/8410 devices. only on PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin).
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PIC18F6310/6410/8310/8410 TABLE 11-17: PORTJ FUNCTIONS Pin Name RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Function TRIS Setting I/O I/O Type RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input.
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PIC18F6310/6410/8310/8410 11.10 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: For PIC18F8310/8410 devices, the Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
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PIC18F6310/6410/8310/8410 REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full S
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PIC18F6310/6410/8310/8410 FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 66 LATD LATD Output Latch Register TRISD PORTD Data Direction Register PORTE RE7 RE6 RE5 66 66 RE4 RE3 RE2 RE1 RE0 66 LATE LATE Output Latch Register
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PIC18F6310/6410/8310/8410 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software-selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit software-programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
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PIC18F6310/6410/8310/8410 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default, unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
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PIC18F6310/6410/8310/8410 12.3 12.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 154  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 13.
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PIC18F6310/6410/8310/8410 13.1 cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
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PIC18F6310/6410/8310/8410 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer.
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PIC18F6310/6410/8310/8410 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
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PIC18F6310/6410/8310/8410 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h ; Preload TMR1 register pair TMR1H ; for 1 second overflow TMR1L b‘00001111’ ; Configure for external clock, T1CON ; Asynchronous operation, external oscillator secs ; Initialize timekeeping registers mins ; .
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 160  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 14.0 TIMER2 MODULE 14.
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PIC18F6310/6410/8310/8410 14.2 Timer2 Interrupt 14.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
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PIC18F6310/6410/8310/8410 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software-selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external), with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1.
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PIC18F6310/6410/8310/8410 15.1 cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous counter • Asynchronous counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
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PIC18F6310/6410/8310/8410 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 166  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6310/6410/8310/8410 devices have three CCP (Capture/Compare/PWM) modules, labelled CCP1, CCP2 and CCP3. All modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. REGISTER 16-1: Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
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PIC18F6310/6410/8310/8410 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.
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PIC18F6310/6410/8310/8410 16.2 16.2.1 Capture Mode In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration).
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PIC18F6310/6410/8310/8410 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit, CCP2IE (PIE2<1>), clear to avoid false interrupts and should clear the flag bit, CCP2IF, following any such change in operating mode. 16.2.4 Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler.
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PIC18F6310/6410/8310/8410 FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger (Timer1/Timer3 Reset) T3CCP2 Comparator 1 CCPR1H TMR1H TMR1L T3CCP1 TMR3H TMR3L 0 CCP1 Pin Set CCP1IF 0 Compare Match Output Logic S Q R TRIS Output Enable 4 CCP1CON<3:0> CCPR1L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) Set CCP2IF Comparator 1 CCPR2H Compare Match CCP2 Pin Output Logic S Q R TRIS Output Enable 4 CCP2CON<3:0> CCPR2L T3CCP1 T3CCP2 Set CCP3IF CCP3 Pin
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PIC18F6310/6410/8310/8410 TABLE 16-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 63 RCON IPEN SBOREN — RI TO PD POR BOR 64 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 P
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PIC18F6310/6410/8310/8410 16.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP2 pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. A PWM output (Figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
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PIC18F6310/6410/8310/8410 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits. Up to 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>.
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PIC18F6310/6410/8310/8410 TABLE 16-4: Name INTCON REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 RCON IPEN SBOREN — RI TO PD POR BOR 64 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TRISB PORTB Data Dir
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PIC18F6310/6410/8310/8410 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC18F6310/6410/8310/8410 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
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PIC18F6310/6410/8310/8410 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmittin
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PIC18F6310/6410/8310/8410 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
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PIC18F6310/6410/8310/8410 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
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PIC18F6310/6410/8310/8410 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
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PIC18F6310/6410/8310/8410 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
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PIC18F6310/6410/8310/8410 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 bit 6 bit
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PIC18F6310/6410/8310/8410 17.3.8 SLEEP OPERATION 17.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 3.7 “Clock Sources and Oscillator Switching” for additional information.
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PIC18F6310/6410/8310/8410 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
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PIC18F6310/6410/8310/8410 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled f
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PIC18F6310/6410/8310/8410 SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) REGISTER 17-4: R/W-0 SMP R/W-0 CKE R/W-0 D/A R/W-0 R/W-0 (1) P (1) S R/W-0 R/W (2,3) R/W-0 R/W-0 UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specifi
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PIC18F6310/6410/8310/8410 SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) REGISTER 17-5: R/W-0 GCEN R/W-0 R/W-0 (1) ACKSTAT ACKDT R/W-0 (2) ACKEN R/W-0 (2) RCEN R/W-0 (2) PEN R/W-0 (2) RSEN R/W-0 SEN(2) bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave
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PIC18F6310/6410/8310/8410 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
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PIC18F6310/6410/8310/8410 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set.
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DS39635C-page 192 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS39635C-page 194 2 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in
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PIC18F6310/6410/8310/8410 17.4.4 CLOCK STRETCHING Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
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PIC18F6310/6410/8310/8410 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
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DS39635C-page 198 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs
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 2010 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
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PIC18F6310/6410/8310/8410 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
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PIC18F6310/6410/8310/8410 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
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PIC18F6310/6410/8310/8410 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
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PIC18F6310/6410/8310/8410 17.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
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PIC18F6310/6410/8310/8410 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
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PIC18F6310/6410/8310/8410 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
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PIC18F6310/6410/8310/8410 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
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PIC18F6310/6410/8310/8410 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification Parameter #106).
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DS39635C-page 208 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Da
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PIC18F6310/6410/8310/8410 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
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PIC18F6310/6410/8310/8410 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.
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PIC18F6310/6410/8310/8410 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
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PIC18F6310/6410/8310/8410 FIGURE 17-27: BUS COLLISION DURING A START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
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PIC18F6310/6410/8310/8410 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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PIC18F6310/6410/8310/8410 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31).
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PIC18F6310/6410/8310/8410 TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 IPR1 TRISC PORTC Data Direction Register 66 SSPBUF Master Synchronous Ser
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PIC18F6310/6410/8310/8410 18.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) PIC18F6310/6410/8310/8410 devices have three serial I/O modules: the MSSP module, discussed in the previous chapter and two Universal Synchronous Asynchronous Receiver Transmitter (USART) modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.
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PIC18F6310/6410/8310/8410 REGISTER 18-1: R/W-0 TXSTA1: EUSART1 TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC TX9 R/W-0 TXEN (1) R/W-0 R/W-0 R/W-0 R-1 R/W-0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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PIC18F6310/6410/8310/8410 REGISTER 18-2: RCSTA1: EUSART1 RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled 0 = Serial port is disabled bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit
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PIC18F6310/6410/8310/8410 REGISTER 18-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0
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PIC18F6310/6410/8310/8410 18.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>) selects 16-bit mode. The SPBRGH1:SPBRG1 register pair controls the period of a free running timer. In Asynchronous mode, bits, BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>), also control the baud rate. In Synchronous mode, BRGH is ignored.
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PIC18F6310/6410/8310/8410 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 2.441 1.73 255 9.615 0.16 64 19.2 19.531 1.73 57.6 56.818 115.2 125.000 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — — — 1.73 255 1.202 2.404 0.16 129 9.766 1.73 31 31 19.531 1.73 -1.36 10 62.500 8.51 4 104.167 Actual Rate (K) % Error 0.
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PIC18F6310/6410/8310/8410 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.
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PIC18F6310/6410/8310/8410 18.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSART state machine is held in Idle.
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PIC18F6310/6410/8310/8410 FIGURE 18-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h 001Ch Start RX1 Pin Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RC1IF bit (Interrupt) Read RCREG1 SPBRG1 XXXXh 1Ch SPBRGH1 XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
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PIC18F6310/6410/8310/8410 18.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA1<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first.
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PIC18F6310/6410/8310/8410 FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TX1IF TXREG1 Register TX1IE 8 MSb LSb (8) Pin Buffer and Control 0  TSR Register TX1 pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH1 SPBRG1 TX9D Baud Rate Generator FIGURE 18-4: Write to TXREG1 BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TX1 (pin) Start bit FIGURE 18-5: bit 0 bit 1 bit 7/8 Stop bit Word 1 TX1IF bit (Transmit Buffer Reg.
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PIC18F6310/6410/8310/8410 TABLE 18-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 TXREG1 TXSTA1 GIE/GIEH PE
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PIC18F6310/6410/8310/8410 18.2.2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 18-6. The data is received on the RX1 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. The RXDTP bit (BAUDCON<5>) allows the RX signal to be inverted (polarity reversed).
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PIC18F6310/6410/8310/8410 FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH1 SPBRG1 Baud Rate Generator  64 or  16 or 4 RSR Register MSb Stop (8)  7 LSb 1 0 Start RX9 Pin Buffer and Control Data Recovery RX1 RX9D RCREG1 Register FIFO SPEN 8 Interrupt RC1IF Data Bus RC1IE FIGURE 18-7: RX1 (pin) Rcv Shift Reg Rcv Buffer Reg RCREG1 Read Rcv Buffer Reg ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit Word 1 R
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PIC18F6310/6410/8310/8410 TABLE 18-6: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 RCREG1 GIE/GIEH PEIE/GIEL TMR0IE Bi
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PIC18F6310/6410/8310/8410 18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up, due to activity on the RX1/DT1 line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
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PIC18F6310/6410/8310/8410 FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit RX1/DT1 Line RC1IF Cleared due to user read of RCREG1 The EUSART remains in Idle while the WUE bit is set.
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PIC18F6310/6410/8310/8410 18.2.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
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PIC18F6310/6410/8310/8410 18.3 Once the TXREG1 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG1 is empty and the TX1IF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is set regardless of the state of enable bit, TX1IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG1 register.
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PIC18F6310/6410/8310/8410 FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 Reg TX1IF bit TRMT bit TXEN bit TABLE 18-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE A
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PIC18F6310/6410/8310/8410 18.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 4. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA1<5>), or the Continuous Receive Enable bit, CREN (RCSTA1<4>). Data is sampled on the RX1 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
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PIC18F6310/6410/8310/8410 TABLE 18-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 RCREG1 TXSTA1 GIE/GIEH
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PIC18F6310/6410/8310/8410 18.4 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.
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PIC18F6310/6410/8310/8410 18.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F6310/6410/8310/8410 19.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is very similar in function to the Enhanced USART module, discussed in the previous chapter. It is provided as an additional channel for serial communication with external devices, for those situations that do not require Auto-Baud Detection (ABD) or LIN/J2602 bus support.
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PIC18F6310/6410/8310/8410 REGISTER 19-1: TXSTA2: AUSART2 TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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PIC18F6310/6410/8310/8410 REGISTER 19-2: RCSTA2: AUSART2 RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabl
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PIC18F6310/6410/8310/8410 19.1 AUSART Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit generator that supports both the Asynchronous and Synchronous modes of the AUSART. The SPBRG2 register controls the period of a free-running timer. In Asynchronous mode, BRGH bit (TXSTA<2>) also controls the baud rate. In Synchronous mode, BRGH is ignored. Table 19-1 shows the formula for computation of the baud rate for different AUSART modes, which only apply in Master mode (internally generated clock).
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PIC18F6310/6410/8310/8410 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES BRGH = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — 1.221 — 1.73 1.73 255 2.404 0.16 64 9.766 19.531 1.73 31 57.6 56.818 -1.36 115.2 125.000 8.51 BAUD RATE (K) Actual Rate (K) % Error 0.3 1.2 — — — — 2.4 2.441 9.6 9.615 19.2 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 255 — 1.202 — 0.16 0.16 129 2.404 1.73 31 9.766 19.531 1.73 15 10 62.
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PIC18F6310/6410/8310/8410 19.2 interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF will be set regardless of the state of TX2IE; it cannot be cleared in software. TX2IF is also not cleared immediately upon loading TXREG2, but becomes valid in the second instruction cycle following the load instruction. Polling TX2IF immediately following a load of TXREG2 will return invalid results.
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PIC18F6310/6410/8310/8410 FIGURE 19-2: ASYNCHRONOUS TRANSMISSION Write to TXREG2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX2IF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 19-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG2 Word 1 Word 2 BRG Output (Shift Clock) TX2 (pin) Start bit bit 1 1 TCY TX2IF bit (Interrupt Reg.
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PIC18F6310/6410/8310/8410 19.2.2 AUSART ASYNCHRONOUS RECEIVER 19.2.3 The receiver block diagram is shown in Figure 19-4. The data is received on the RX2 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
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PIC18F6310/6410/8310/8410 FIGURE 19-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX2 (pin) bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG2 Word 1 RCREG2 Read Rcv Buffer Reg RCREG2 bit 7/8 RC2IF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer 2) is read after the third word, causing the OERR (Overrun) bit to be set.
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PIC18F6310/6410/8310/8410 19.3 Once the TXREG2 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG2 is empty and the TX2IF flag bit (PIR3<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is set regardless of the state of enable bit, TX2IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG2 register.
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PIC18F6310/6410/8310/8410 FIGURE 19-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX2/DT2 Pin bit 0 bit 1 bit 2 bit 6 bit 7 TX2/CK2 Pin Write to TXREG2 Reg TX2IF bit TRMT bit TXEN bit TABLE 19-6: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 6
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PIC18F6310/6410/8310/8410 19.3.2 AUSART SYNCHRONOUS MASTER RECEPTION 4. 5. 6. If interrupts are desired, set enable bit, RC2IE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RC2IF, will be set when reception is complete and an interrupt will be generated if the enable bit, RC2IE, was set. 8.
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PIC18F6310/6410/8310/8410 19.4 AUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA2<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK2 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.4.
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PIC18F6310/6410/8310/8410 19.4.2 AUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep, or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep, or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F6310/6410/8310/8410 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 12 inputs for the PIC18FX310/X410 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
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PIC18F6310/6410/8310/8410 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-q R/W-q R/W-q R/W-q — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared AN2 AN1 AN0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AN3 0000 AN4 PCFG<3:0> AN5 PCFG<3:0>: A/D Port Configuration Control bits: AN6 bit 3-0
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PIC18F6310/6410/8310/8410 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 T
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PIC18F6310/6410/8310/8410 The analog reference voltage is software-selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O.
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PIC18F6310/6410/8310/8410 Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For next conversion, go to Step 1 or Step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 3 TAD is required before the next acquisition starts. 6. 7. FIGURE 20-2: 3FFh 1. 3FEh FIGURE 20-3: 002h 001h 1023 LSB 1023.5 LSB 1022 LSB 1022.
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PIC18F6310/6410/8310/8410 20.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F6310/6410/8310/8410 20.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. Acquisition time may be set with the ACQT<2:0> bits (ADCON2<5:3>), which provides a range of 2 to 20 TAD.
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PIC18F6310/6410/8310/8410 20.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started.
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PIC18F6310/6410/8310/8410 20.6 After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. A/D Conversions Figure 20-4 shows the operation of the A/D Converter after the GO bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F6310/6410/8310/8410 20.8 Use of the CCP2 Trigger An A/D conversion can be started by the “Special Event Trigger” of the CCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero.
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PIC18F6310/6410/8310/8410 21.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RF3 through RF6, as well as the on-chip voltage reference (see Section 22.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
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PIC18F6310/6410/8310/8410 21.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 21-1. Bits, CM<2:0>, of the CMCON register are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode.
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PIC18F6310/6410/8310/8410 21.2 21.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
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PIC18F6310/6410/8310/8410 + To RA4 or RA5 Pin - Port Pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 21-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
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PIC18F6310/6410/8310/8410 21.9 range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 21-4.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 270  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 22.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram is of the module shown in Figure 22-1.
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PIC18F6310/6410/8310/8410 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 22.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 22-1) keep CVREF from approaching the reference source rails.
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PIC18F6310/6410/8310/8410 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 22-1: Name CVRCON CMCON TRISF + – RF5 CVREF Output R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 274  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 23.0 The High/Low-Voltage Detect Control register (Register 23-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F6310/6410/8310/8410 devices have a High/Low-Voltage Detect module (HLVD).
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PIC18F6310/6410/8310/8410 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. level at which the device detects a high or low-voltage event, depending on the configuration of the module.
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PIC18F6310/6410/8310/8410 23.2 Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. HLVD Setup The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>).
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PIC18F6310/6410/8310/8410 FIGURE 23-3: HIGH/LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, the ability to detect a drop below, or rise above, a particular thr
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PIC18F6310/6410/8310/8410 23.6 Operation During Sleep 23.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 280  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 24.0 A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. SPECIAL FEATURES OF THE CPU In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F6310/6410/8310/8410 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits, or software controlled (if configured as disabled).
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PIC18F6310/6410/8310/8410 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode is enabled 0 = Oscillator Switchover
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PIC18F6310/6410/8310/8410 REGISTER 24-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — — U-0 — R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOREN1 R/P-1 (1) BOREN0 R/P-1 (1) PWRTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits 11 = Minimum setting • • • 00 = Maxi
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PIC18F6310/6410/8310/8410 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 110
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PIC18F6310/6410/8310/8410 REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/P-1 R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT BW — — — — PM1 PM0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections are unavailable, device will not wait 0 = Wait is programmed by the WAIT1 and
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PIC18F6310/6410/8310/8410 REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 U-0 R/P-1 MCLRE — — — — LPT1OSC — CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RG5 input pin is disabled 0 = RG5 input pin is enabled; MCLR is disabled bit 6
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PIC18F6310/6410/8310/8410 REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 U-0 U-0 U-0 R/P-1 DEBUG XINST — — — — — STVREN bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed bit u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins 0 = Backgro
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PIC18F6310/6410/8310/8410 REGISTER 24-8: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 — — — — — — — EBTR(2,3) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed bit U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-1 Unimplemented: Read as ‘0 bit 0 EBTR: Table Read Protection bit(2,3) 1= Internal program memory block is not protected from table reads executed
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PIC18F6310/6410/8310/8410 REGISTER 24-9: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6310/6410/8310/8410 DEVICES R R R R R R R R DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 DEV<2:0>: Device ID bits(1) 110 = PIC18F8310, PIC18F8410 111 = PIC18F6310, PIC18F6410 bit 4-0 REV<4:0>: Revision ID bits These bits are used to ind
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PIC18F6310/6410/8310/8410 24.2 Watchdog Timer (WDT) For PIC18F6310/6410/8310/8410 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
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PIC18F6310/6410/8310/8410 REGISTER 24-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the C
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PIC18F6310/6410/8310/8410 24.3 In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available.
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PIC18F6310/6410/8310/8410 24.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
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PIC18F6310/6410/8310/8410 FIGURE 24-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 24.4.3 CM Test CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
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PIC18F6310/6410/8310/8410 24.5 Program Verification and Code Protection The overall structure of the code protection on the PIC18F6310/6410/8310/8410 Flash devices differs from previous PIC18 devices. For all devices in the PIC18FX310/X410 family, the user program memory is made of a single block. Figure 24-5 shows the program memory organization for individual devices. Code protection for this block is controlled by a single bit, CP (CONFIG5L<0>).
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PIC18F6310/6410/8310/8410 24.6 ID Locations 24.8 In-Circuit Debugger Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are readable during normal execution through the TBLRD instruction. During program/verify, these locations are readable and writable. The ID locations can be read when the device is code-protected.
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PIC18F6310/6410/8310/8410 25.0 INSTRUCTION SET SUMMARY PIC18F6310/6410/8310/8410 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.
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PIC18F6310/6410/8310/8410 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f.
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PIC18F6310/6410/8310/8410 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
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PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f
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PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
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PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtr
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PIC18F6310/6410/8310/8410 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) + (f)  dest Status Affected: N, OV, C, DC, Z k Operands: 0  k  255 Operation: (W) + k  W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
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PIC18F6310/6410/8310/8410 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0  f  255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C)  dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
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PIC18F6310/6410/8310/8410 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0  f  255 d [0,1] a [0,1] Operands: -128  n  127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f)  dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F6310/6410/8310/8410 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0  f  255 0b7 a [0,1] Operands: -128  n  127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None f, b {,a} Operation: 0  f Status Affected: None Encoding: 1001 Description: Encoding: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6310/6410/8310/8410 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n  PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch.
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PIC18F6310/6410/8310/8410 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n  PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch.
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PIC18F6310/6410/8310/8410 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024  n  1023 Operands: Operation: (PC) + 2 + 2n  PC Status Affected: None 0  f  255 0b7 a [0,1] Operation: 1  f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
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PIC18F6310/6410/8310/8410 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 0b7 a [0,1] Operands: 0  f  255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff Encoding: 1010 bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
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PIC18F6310/6410/8310/8410 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0  f  255 0b<7 a [0,1] Operands: -128  n  127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None Operation: (f)  f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6310/6410/8310/8410 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128  n  127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC 0  k  1048575 s [0,1] Operation: Status Affected: None (PC) + 4  TOS, k  PC<20:1>, if s = 1 (W)  WS, (STATUS)  STATUSS, (BSR)  BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
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PIC18F6310/6410/8310/8410 CLRF Clear f Syntax: CLRF Operands: 0  f  255 a [0,1] f {,a} Operation: 000h  f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.
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PIC18F6310/6410/8310/8410 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0  f  255 a  [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0  f  255 d  [0,1] a  [0,1] Operands: Operation: ( f )  dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F6310/6410/8310/8410 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0  f  255 a  [0,1] Operands: 0  f  255 a  [0,1] Operation: (f) W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of
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PIC18F6310/6410/8310/8410 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then, (W<3:0>) + 6  W<3:0>; else, (W<3:0>)  W<3:0>; 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then, (W<7:4>) + 6  W<7:4>, C =1; else, (W<7:4>)  W<7:4> Status Affected: 0000 0000 0000 DAW adjusts the eight-bit value in W, resu
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PIC18F6310/6410/8310/8410 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest, skip if result = 0 Operation: (f) – 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F6310/6410/8310/8410 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0  k  1048575 Operands: Operation: k  PC<20:1> Status Affected: None 0  f  255 d  [0,1] a  [0,1] Operation: (f) + 1  dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No o
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PIC18F6310/6410/8310/8410 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0  f  255 d  [0,1] a  [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: Operation: (f) + 1  dest, skip if result = 0 Operation: (f) + 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 Description: 10da ffff ffff The contents of register ‘f’ are incremented
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PIC18F6310/6410/8310/8410 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0  k  255 Operands: Operation: (W) .OR. k  W Status Affected: N, Z 0  f  255 d  [0,1] a  [0,1] Operation: (W) .OR. (f)  dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
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PIC18F6310/6410/8310/8410 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0  k  4095 Operands: Operation: k  FSRf 0  f  255 d  [0,1] a  [0,1] Status Affected: None Operation: f  dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
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PIC18F6310/6410/8310/8410 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0  fs  4095 0  fd  4095 Operands: 0  k  255 Operation: k  BSR None Operation: (fs)  fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
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PIC18F6310/6410/8310/8410 MOVLW Move literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0  k  255 Operands: Operation: kW 0  f  255 a  [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
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PIC18F6310/6410/8310/8410 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0  f  255 a  [0,1] Operation: (W) x (f)  PRODH:PRODL Status Affected: None k Operands: 0  k  255 Operation: (W) x k  PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair.
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PIC18F6310/6410/8310/8410 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0  f  255 a  [0,1] f {,a} Operands: None Operation: No operation None Operation: (f)+1f Status Affected: Status Affected: N, OV, C, DC, Z Encoding: Encoding: 0110 Description: 110a ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6310/6410/8310/8410 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
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PIC18F6310/6410/8310/8410 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, (PC) + 2 + 2n  PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
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PIC18F6310/6410/8310/8410 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, 1  GIE/GIEH or PEIE/GIEL; if s = 1, (WS)  W, (STATUSS)  STATUS, (BSRS)  BSR, PCLATU, PCLATH are unchanged Operation: k  W, (TOS)  PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded
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PIC18F6310/6410/8310/8410 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s  [0,1] Operands: Operation: (TOS)  PC; if s = 1, (WS)  W, (STATUSS)  STATUS, (BSRS)  BSR, PCLATU, PCLATH are unchanged 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f<7>)  C, (C)  dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Encoding: 0000 0001 001s Description: Return from subroutine.
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PIC18F6310/6410/8310/8410 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f<7>)  dest<0> Operation: Status Affected: N, Z (f)  dest, (f<0>)  C, (C)  dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
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PIC18F6310/6410/8310/8410 RRNCF Rotate Right f (no carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 a [0,1] Operation: FFh  f Operation: (f)  dest, (f<0>)  dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F6310/6410/8310/8410 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h  WDT, 0  WDT postscaler, 1  TO, 0  PD 0 f 255 d  [0,1] a  [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
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PIC18F6310/6410/8310/8410 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d  [0,1] a  [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
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PIC18F6310/6410/8310/8410 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>)  dest<7:4>, (f<7:4>)  dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
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PIC18F6310/6410/8310/8410 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR))  TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR))  TABLAT, (TBLPTR) + 1  TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT, (TBLPTR) – 1  TBLPTR; if TBLRD +*, (TBLPTR) + 1  TBLPTR, (Prog Mem (TBLPTR))  TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: St
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PIC18F6310/6410/8310/8410 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT)  Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT)  Holding Register, (TBLPTR) + 1  TBLPTR; if TBLWT*-, (TABLAT)  Holding Register, (TBLPTR) – 1  TBLPTR; if TBLWT+*, (TBLPTR) + 1  TBLPTR, (TABLAT)  Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLP
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PIC18F6310/6410/8310/8410 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 a  [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a two-cycle instruction.
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PIC18F6310/6410/8310/8410 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6310/6410/8310/8410 25.2 Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F6310/6410/8310/8410 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing for many of the standard PIC18 instructions.
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PIC18F6310/6410/8310/8410 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 f  [0, 1, 2] Operands: 0  k  63 Operation: FSR(f) + k  FSR(f) Status Affected: None Encoding: 1110 FSR2 + k  FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
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PIC18F6310/6410/8310/8410 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2)  TOS, (W)  PCL, (PCLATH)  PCH, (PCLATU)  PCU 0  zs  127 0  fd  4095 Operation: ((FSR2) + zs)  fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
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PIC18F6310/6410/8310/8410 MOVSS Move Indexed to Indexed PUSHL Syntax: Store Literal at FSR2, Decrement FSR2 Operands: MOVSS [zs], [zd] 0  zs  127 0  zd  127 Syntax: PUSHL k Operands: 0k  255 Operation: ((FSR2) + zs)  ((FSR2) + zd) Operation: Status Affected: None k  (FSR2), FSR2 - 1 FSR2 Status Affected: None Encoding: 1st word (source) 2nd word (dest.
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PIC18F6310/6410/8310/8410 SUBFSR Subtract Literal from FSR Syntax: SUBFSR f, k Subtract Literal from FSR2 and Return SUBULNK 0  k  63 Syntax: SUBULNK k f  [ 0, 1, 2 ] Operands: 0  k  63 Operation: FSRf – k  FSRf Operation: Status Affected: None Operands: Encoding: 1110 Description: 1001 ffkk kkkk The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
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PIC18F6310/6410/8310/8410 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset addressing (Section 6.5.1 “Indexed Addressing with Literal Offset”).
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PIC18F6310/6410/8310/8410 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0  k  95 d  [0,1] Operands: 0  f  95 0b7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by t
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PIC18F6310/6410/8310/8410 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F6310/6410/8310/8410 family of devices. This includes the MPLAB C18 compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
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PIC18F6310/6410/8310/8410 26.
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PIC18F6310/6410/8310/8410 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
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PIC18F6310/6410/8310/8410 26.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC18F6310/6410/8310/8410 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC18F6310/6410/8310/8410 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ........................................
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PIC18F6310/6410/8310/8410 FIGURE 27-1: PIC18F6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V PIC18F6310/6410 PIC18F8310/8410 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20 MHz in 8-bit External Memory mode. FMAX = 40 MHz in all other modes. FIGURE 27-2: PIC18F6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V 4.5V PIC18F6310/6410 PIC18F8310/8410 4.2V 4.0V 3.5V 3.0V 2.5V 2.
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PIC18F6310/6410/8310/8410 FIGURE 27-3: PIC18LF6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V PIC18LF6310/6410 PIC18LF8310/8410 Voltage 5.0V 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX 4 MHz Frequency In 8-bit External Memory mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. In all other modes: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
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PIC18F6310/6410/8310/8410 27.
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PIC18F6310/6410/8310/8410 27.3 DC Characteristics: PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V  VDD 5.
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PIC18F6310/6410/8310/8410 27.3 DC Characteristics: PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.
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PIC18F6310/6410/8310/8410 TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions 10.0 — 12.
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PIC18F6310/6410/8310/8410 TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated. Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
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PIC18F6310/6410/8310/8410 FIGURE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD VDD For VDIRMAG = 0: HLVDIF TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial Param Symbol No. D420 D420B VBG Characteristic Min Typ† Max Units HLVD Voltage on VDD LVV = 0000 Transition LVV = 0001 1.80 1.
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PIC18F6310/6410/8310/8410 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
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PIC18F6310/6410/8310/8410 27.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-5 specifies the load conditions for the timing specifications. TABLE 27-5: Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F6310/6410/ 8310/8410 and PIC18LF6310/6410/8310/ 8410 families of devices specifically and only those devices.
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PIC18F6310/6410/8310/8410 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 1 MHz DC 25 MHz HS Oscillator mode DC 31.
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PIC18F6310/6410/8310/8410 TABLE 27-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25C, unless otherwise stated.
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PIC18F6310/6410/8310/8410 FIGURE 27-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 TABLE 27-9: Param No.
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PIC18F6310/6410/8310/8410 FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 AD<19:16> BA0 Address Address Address AD<15:0> Data from External 150 151 Address 163 160 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 TABLE 27-10: PROGRAM MEMORY READ TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.
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PIC18F6310/6410/8310/8410 FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 AD<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.
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PIC18F6310/6410/8310/8410 FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins FIGURE 27-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param.
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PIC18F6310/6410/8310/8410 FIGURE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 TABLE 27-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width 41 TT0L T0CKI Low Pulse Width 42 TT0P T0CKI Period No prescaler With prescaler No prescaler With prescaler 45 TT1H ns 10 — ns 0.
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PIC18F6310/6410/8310/8410 FIGURE 27-13: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 27-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With PIC18FXXXX prescaler PIC18LFXXXX 0.5 TCY + 20 — ns 10 — ns 20 — ns CCPx Input High Time 0.
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PIC18F6310/6410/8310/8410 FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
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PIC18F6310/6410/8310/8410 FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDI MSb In 74 TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
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PIC18F6310/6410/8310/8410 FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 MSb In SDI 77 bit 6 - - - - 1 LSb In 74 73 TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic Min 70 TSSL2SCH, SS  to SCK  or SCK  Input TSSL2SCL 71 TSCH SCK Input High Time Continuous TSCL SCK Input Low Time 71A 72 72A TCY — ns 1.
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PIC18F6310/6410/8310/8410 FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In 77 bit 6 - - - - 1 LSb In 74 TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min 70 TSSL2SCH, SS  to SCK  or SCK  Input TSSL2SCL 71 TSCH SCK Input High Time TSCL SCK Input Low Time 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.
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PIC18F6310/6410/8310/8410 FIGURE 27-18: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition TABLE 27-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
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PIC18F6310/6410/8310/8410 TABLE 27-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 THD:STA 91 THD:DAT 106 TSU:DAT 107 TSU:STO 92 109 TAA 110 TBUF D102 CB Note 1: 2: Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 — s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXXXX must operate at a minimum of 10 MHz MSSP Module 1.5 TCY — 100 kHz mode 4.
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PIC18F6310/6410/8310/8410 FIGURE 27-20: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition TABLE 27-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
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PIC18F6310/6410/8310/8410 TABLE 27-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
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PIC18F6310/6410/8310/8410 FIGURE 27-22: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 122 TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
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PIC18F6310/6410/8310/8410 TABLE 27-25: A/D CONVERTER CHARACTERISTICS: PIC18F6310/6410/8310/8410 (INDUSTRIAL) PIC18LF6310/6410/8310/8410 (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units — — 10 bit Conditions VREF  3.0V A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb VREF  3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF  3.0V A06 EOFF Offset Error — — <±1 LSb VREF  3.0V A07 EGN Gain Error — — <±1 LSb VREF  3.
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PIC18F6310/6410/8310/8410 FIGURE 27-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 132 (1) 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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PIC18F6310/6410/8310/8410 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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PIC18F6310/6410/8310/8410 28.2 Package Details The following sections give the technical details of the packages.
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PIC18F6310/6410/8310/8410 ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 ) ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 12 3 NOTE 2 c φ β L α A A2 A1 L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : @ / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4
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PIC18F6310/6410/8310/8410 ) ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 394  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 APPENDIX A: REVISION HISTORY Revision A (June 2004) Original data sheet for PIC18F6310/6410/8310/8410 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (May 2007) Updated Electrical Characteristics and packaging diagrams. Revision C (October 2010) Changes to electricals in Section 27.0 “Electrical Characteristics” and minor text edits throughout document.
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PIC18F6310/6410/8310/8410 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.
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PIC18F6310/6410/8310/8410 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
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PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 398  2010 Microchip Technology Inc.
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PIC18F6310/6410/8310/8410 INDEX A A/D ................................................................................... 255 A/D Converter Interrupt, Configuring ....................... 259 Acquisition Requirements ........................................ 260 ADCON0 Register .................................................... 255 ADCON1 Register .................................................... 255 ADCON2 Register .................................................... 255 ADRESH Register ................
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PIC18F6310/6410/8310/8410 RCIO Oscillator Mode ................................................ 37 Reads From Program Memory .................................. 91 Single Comparator ................................................... 267 Table Read and Table Write Operations ................... 89 Timer0 in 16-Bit Mode .............................................. 152 Timer0 in 8-Bit Mode ................................................ 152 Timer1 ............................................................
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PIC18F6310/6410/8310/8410 Data Memory ..................................................................... 75 Access Bank .............................................................. 77 and the Extended Instruction Set ............................... 86 Bank Select Register (BSR) ....................................... 75 General Purpose Registers ........................................ 77 Map for PIC18F6310/6410/8310/8410 Devices ......... 76 Special Function Registers .................................
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PIC18F6310/6410/8310/8410 I I/O Ports ........................................................................... 125 I2C Mode (MSSP) Acknowledge Sequence Timing ............................... 210 Associated Registers ............................................... 216 Baud Rate Generator ............................................... 203 Bus Collision During a Repeated Start Condition .................. 214 During a Start Condition ................................... 212 During a Stop Condition .........
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PIC18F6310/6410/8310/8410 TBLRD ..................................................................... 335 TBLWT ..................................................................... 336 TSTFSZ ................................................................... 337 XORLW .................................................................... 337 XORWF .................................................................... 338 Summary Table ........................................................
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PIC18F6310/6410/8310/8410 RA4/T0CKI ........................................................... 15, 23 RA5/AN4/HLVDIN ................................................ 15, 23 RB0/INT0 ............................................................. 16, 24 RB1/INT1 ............................................................. 16, 24 RB2/INT2 ............................................................. 16, 24 RB3/INT3 ................................................................... 16 RB3/INT3/CCP2 ..........
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PIC18F6310/6410/8310/8410 PORTF Associated Registers ............................................... 141 Functions ................................................................. 141 LATF Register .......................................................... 140 PORTF Register ...................................................... 140 TRISF Register ........................................................ 140 PORTG Associated Registers ............................................... 143 Functions ...........
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PIC18F6310/6410/8310/8410 HLVDCON (HLVD Control) ...................................... 275 INTCON (Interrupt Control) ...................................... 111 INTCON2 (Interrupt Control 2) ................................. 112 INTCON3 (Interrupt Control 3) ................................. 113 IPR1 (Peripheral Interrupt Priority 1) ........................ 120 IPR2 (Peripheral Interrupt Priority 2) ........................ 121 IPR3 (Peripheral Interrupt Priority 3) ........................
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PIC18F6310/6410/8310/8410 Timer0 .............................................................................. 151 16-Bit Mode Timer Reads and Writes ...................... 152 Associated Registers ............................................... 153 Clock Source Edge Select (T0SE Bit) ...................... 152 Clock Source Select (T0CS Bit) ............................... 152 Operation ................................................................. 152 Overflow Interrupt ................................
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PIC18F6310/6410/8310/8410 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ....................... 60 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ....................... 60 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 60 Timer0 and Timer1 External Clock .......................... 376 Transition for Entry to PRI_IDLE Mode ...................... 51 Transition for Entry to SEC_RUN Mode .................... 47 Transition for Entry to Sleep Mode ...
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PIC18F6310/6410/8310/8410 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F6310/6410/8310/8410 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F6310/6410/8310/8410 PIC18F6310/6410/8310/8410 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F6310/6410/8310/8410(1), PIC18F6310/6410/8310/8410T(2); VDD range 4.2V to 5.5V PIC18LF6310/6410/8310/8410(1), PIC18LF6310/6410/8310/8410T(2); VDD range 2.0V to 5.
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