Datasheet

 2010 Microchip Technology Inc. DS39635C-page 95
PIC18F6310/6410/8310/8410
8.0 EXTERNAL MEMORY
INTERFACE
The external memory interface allows the device to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory. It is
implemented with 28 pins, multiplexed across four I/O
ports. Three ports (PORTD, PORTE and PORTH) are
multiplexed with the address/data bus for a total of 20
available lines, while PORTJ is multiplexed with the
bus control signals. A list of the pins and their functions
is provided in Table 8-1.
As implemented here, the interface is similar to that
introduced on PIC18F8X20 microcontrollers. The most
notable difference is that the interface on
PIC18F8310/8410 devices supports both 16-Bit and
Multiplexed 8-Bit Data Width modes; it does not sup-
port the 8-Bit Demultiplexed mode. The Bus Width
mode is set by the BW Configuration bit when the
device is programmed and cannot be changed in
software.
The operation of the interface is controlled by the
MEMCON register (Register 8-1). Clearing the EBDIS
bit (MEMCON<7>) enables the interface and disables
the I/O functions of the ports, as well as any other mul-
tiplexed functions. Setting the bit disables the interface
and enables the ports.
For a more complete discussion of the operating
modes that use the external memory interface, refer to
Section 8.1 “Program Memory Modes and the
External Memory Interface”.
Note: The external memory interface is not
implemented on PIC18F6310 and
PIC18F6410 (64-pin) devices.
REGISTER 8-1: MEMCON: MEMORY CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EBDIS
—WAIT1WAIT0— —WM1WM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EBDIS: External Bus Disable bit
1 = External system bus disabled, all external bus drivers are mapped as I/O ports
0 = External system bus enabled, I/O ports are disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 T
CY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 WM<1:0>: TBLWRT Operation with 16-Bit Bus Width bits
1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1
is written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH
and (UB or LB)
will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.