Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 92  2010 Microchip Technology Inc.
7.4 Writing to Program Memory Space
(PIC18F8310/8410 only)
The table write operation outputs the contents of the
TBLPTR and TABLAT registers to the external address
and data busses of the external memory interface.
Depending on the program memory mode selected, the
operation may target any byte address in the device’s
memory space. What happens to this data depends
largely on the external memory device being used.
For PIC18 devices with Enhanced Flash memory, a
single algorithm is used for writing to the on-chip
program array. In the case of external devices, however,
the algorithm is determined by the type of memory
device and its requirements. In some cases, a specific
instruction sequence must be sent before data can be
written or erased. Address and data demultiplexing,
chip select operation and write time requirements must
all be considered in creating the appropriate code.
The connection of the data and address busses to the
memory device are dictated by the interface being
used, the data bus width and the target device. When
using a 16-bit data path, the algorithm must take into
account the width of the target memory.
Another important consideration is the write time
requirement of the target device. If this is longer than
the time that a TBLWT operation makes data available
on the interface, the algorithm must be adjusted to
lengthen this time. It may be possible, for example, to
buy enough time by increasing the length of the wait
state on table operations.
In all cases, it is important to remember that instruc-
tions in the program memory space are word-aligned,
with the Least Significant bit always being written to an
even-numbered address (LSb = 0). If data is being
stored in the program memory space, word alignment
of the data is not required.
A complete overview of interface algorithms is beyond
the scope of this data sheet. The best place for timing
and instruction sequence requirements is the data
sheet of the memory device in question. For additional
information on algorithm design for the external
memory interface, refer to Microchip application note
AN869, “External Memory Interfacing Techniques for
the PIC18F8XXX” (DS00869).
7.4.1 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.4.2 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the application writes to external
memory on a frequent basis, it may be necessary to
implement an error trapping routine to handle these
unplanned events.
7.5 Erasing External Memory
(PIC18F8310/8410 only)
Erasure is implemented in different ways on different
devices. In many cases, it is possible to erase all or part
of the memory by issuing a specific command. In some
devices, it may be necessary to write ‘0’s to the locations
to be erased. For specific information, consult the
external memory device’s data sheet for clarification.
7.6 Writing and Erasing On-Chip
Program Memory (ICSP Mode)
While the on-chip program memory is read-only in
normal operating mode, it can be written to and erased
as a function of In-Circuit Serial Programming (ICSP). In
this mode, the TBLWT operation is used in all devices to
write to blocks of 64 bytes (32 words) at one time. Write
blocks are boundary-aligned with the code protection
blocks. Special commands are used to erase one or
more code blocks of the program memory, or the entire
device.
The TBLWT operation on write blocks is somewhat
different than the word write operations for
PIC18F8310/8410 devices described here. A more
complete description of block write operations is
provided in the Microchip document “Programming
Specifications for PIC18FX410/X490 Flash MCUs”
(DS39624).
7.7 Flash Program Operation During
Code Protection
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.