Datasheet

 2010 Microchip Technology Inc. DS39635C-page 81
PIC18F6310/6410/8310/8410
SPBRG1 EUSART1 Baud Rate Generator Low Byte 0000 0000 65, 221
RCREG1 EUSART1 Receive Register 0000 0000 65, 229
TXREG1 EUSART1 Transmit Register xxxx xxxx 65, 226
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 65, 218
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 65, 219
IPR3
— — RC2IP TX2IP — — — CCP3IP --11 ---1 65, 122
PIR3
— —RC2IFTX2IF— — — CCP3IF --00 ---0 65, 116
PIE3
— — RC2IE TX2IE — — — CCP3IE --00 ---0 65, 119
IPR2 OSCFIP CMIP
— — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 65, 121
PIR2 OSCFIF CMIF
— — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 65, 115
PIE2 OSCFIE CMIE
— — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 65, 118
IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 65, 120
PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 65, 114
PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 65, 117
MEMCON
(2)
EBDIS —WAIT1WAIT0— —WM1WM00-00 --00 65, 95
OSCTUNE INTSRC PLLEN
(3)
— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 39, 65
TRISJ
(2)
PORTJ Data Direction Register 1111 1111 65, 147
TRISH
(2)
PORTH Data Direction Register 1111 1111 65, 145
TRISG
— — — PORTG Data Direction Register ---1 1111 66, 143
TRISF PORTF Data Direction Register 1111 1111 66, 141
TRISE PORTE Data Direction Register 1111 1111 66, 139
TRISD PORTD Data Direction Register 1111 1111 66, 136
TRISC PORTC Data Direction Register 1111 1111 66, 133
TRISB PORTB Data Direction Register 1111 1111 66, 130
TRISA TRISA7
(5)
TRISA6
(5)
PORTA Data Direction Register 1111 1111 66, 127
LATJ
(2)
LATJ Output Latch Register xxxx xxxx 66, 147
LATH
(2)
LATH Output Latch Register xxxx xxxx 66, 145
LATG
— — — LATG Output Latch Register ---x xxxx 66, 143
LATF LATF Output Latch Register xxxx xxxx 66, 141
LATE LATE Output Latch Register xxxx xxxx 66, 139
LATD LATD Output Latch Register xxxx xxxx 66, 136
LATC LATC Output Latch Register xxxx xxxx 66, 133
LATB LATB Output Latch Register xxxx xxxx 66, 130
LATA LATA7
(5)
LATA6
(5)
LATA Output Latch Register xxxx xxxx 66, 127
PORTJ
(2)
Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 66, 147
PORTH
(2)
Read PORTH pins, Write PORTH Data Latch xxxx xxxx 66, 145
PORTG
— —RG5
(4)
Read PORTG pins<4:0>, Write PORTG Data Latch<4:0> --xx xxxx 66, 143
PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 66, 141
PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 66, 139
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 66, 136
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 66, 133
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 66, 130
PORTA RA7
(5)
RA6
(5)
Read PORTA pins, Write PORTA Data Latch xx0x 0000 66, 127
TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: STKFUL and STKUNF bits are cleared by user software or by a POR.