Datasheet

 2010 Microchip Technology Inc. DS39635C-page 65
PIC18F6310/6410/8310/8410
CCPR1H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu
CCPR2H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu
CCP2CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu
CCPR3H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu
CCP3CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu
CVRCON 6X10 8X10 0000 0000 0000 0000 uuuu uuuu
CMCON 6X10 8X10 0000 0111 0000 0111 uuuu uuuu
TMR3H 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu
TMR3L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu
T3CON 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu
PSPCON 6X10 8X10 0000 ---- 0000 ---- uuuu ----
SPBRG1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu
RCREG1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu
TXREG1 6X10 8X10 xxxx xxxx 0000 0000 uuuu uuuu
TXSTA1 6X10 8X10 0000 0010 0000 0010 uuuu uuuu
RCSTA1 6X10 8X10 0000 000x 0000 000x uuuu uuuu
IPR3 6X10 8X10 --11 ---1 --11 ---1 --uu ---u
PIR3 6X10 8X10 --00 ---0 --00 ---0 --uu ---u
(1)
PIE3 6X10 8X10 --00 ---0 --00 ---0 --uu ---u
IPR2 6X10 8X10 11-- 1111 11-- 1111 uu-- uuuu
PIR2 6X10 8X10 00-- 0000 00-- 0000 uu-- uuuu
(1)
PIE2 6X10 8X10 00-- 0000 00-- 0000 uu-- uuuu
IPR1 6X10 8X10 1111 1111 1111 1111 uuuu uuuu
PIR1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu
(1)
PIE1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu
MEMCON
6X10 8X10 0-00 --00 0-00 --00 u-uu --uu
OSCTUNE 6X10 8X10 00-0 0000 00-0 0000 uu-u uuuu
TRISJ
6X10 8X10 1111 1111 1111 1111 uuuu uuuu
TRISH
6X10 8X10 1111 1111 1111 1111 uuuu uuuu
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.