Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 408  2010 Microchip Technology Inc.
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 1) ....................... 60
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 2) ....................... 60
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise TPWRT) .............. 60
Timer0 and Timer1 External Clock .......................... 376
Transition for Entry to PRI_IDLE Mode ...................... 51
Transition for Entry to SEC_RUN Mode .................... 47
Transition for Entry to Sleep Mode ............................ 50
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 292
Transition for Wake From Idle to Run Mode .............. 51
Transition for Wake From Sleep (HSPLL) ................. 50
Transition From RC_RUN Mode to
PRI_RUN Mode .................................................49
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 47
Transition to RC_RUN Mode ..................................... 49
USART Synchronous Receive (Master/Slave) ........ 386
USART Synchronous Transmission
(Master/Slave) .................................................. 386
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 388
AC Characteristics
Internal RC Accuracy .......................................371
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 377
CLKO and I/O Requirements ................................... 372
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 378
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 379
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 380
Example SPI Slave Mode
Requirements (CKE = 1) .................................. 381
External Clock Requirements .................................. 370
I
2
C Bus Data Requirements (Slave Mode) .............. 383
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 382
Master SSP I
2
C Bus Data Requirements ................ 385
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 384
PLL Clock ................................................................ 371
Program Memory Read Requirements .................... 373
Program Memory Write Requirements .................... 374
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 375
Timer0 and Timer1 External Clock
Requirements .................................................. 376
USART Synchronous Receive Requirements ......... 386
USART Synchronous Transmission
Requirements .................................................. 386
Top-of-Stack Access .......................................................... 70
TRISE Register
PSPMODE Bit .......................................................... 148
TSTFSZ ........................................................................... 337
Two-Speed Start-up ................................................. 281, 292
Two-Word Instructions
Example Cases .......................................................... 74
TXSTA1 Register
BRGH Bit ................................................................. 221
TXSTA2 Register
BRGH Bit ................................................................. 244
V
Voltage Reference Specifications .................................... 366
W
Watchdog Timer (WDT) ........................................... 281, 290
Associated Registers ............................................... 291
Control Register ....................................................... 290
During Oscillator Failure .......................................... 293
Programming Considerations .................................. 290
WCOL ...................................................... 205, 206, 207, 210
WCOL Status Flag ................................... 205, 206, 207, 210
WWW Address ................................................................ 409
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 337
XORWF ........................................................................... 338