Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 380  2010 Microchip Technology Inc.
FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input TCY —ns
71 T
SCH SCK Input High Time Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 T
DOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
76 TDOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS  to SDO Output High-impedance 10 50 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
83 T
SCH2SSH,
T
SCL2SSH
SS
 after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
80
SDI
MSb LSb
bit 6 - - - - - - 1
MSb In
bit 6 - - - - 1 LSb In
83