Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 378  2010 Microchip Technology Inc.
FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input TCY —ns
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
76 T
DOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
79 T
SCF SCK Output Fall Time — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after
SCK Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - - 1
MSb In
LSb In
bit 6 - - - - 1