Datasheet
2010 Microchip Technology Inc. DS39635C-page 295
PIC18F6310/6410/8310/8410
24.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18F6310/6410/8310/8410 Flash devices differs
from previous PIC18 devices.
For all devices in the PIC18FX310/X410 family, the
user program memory is made of a single block.
Figure 24-5 shows the program memory organization
for individual devices. Code protection for this block is
controlled by a single bit, CP (CONFIG5L<0>). The CP
bit inhibits external reads and writes; it has no direct
effect in normal execution mode.
24.5.1 CODE PROTECTION FROM
EXTERNAL TABLE READS
The program memory may be read to any location
using the table read instructions. The Device ID and the
Configuration registers may be read with the table read
instructions.
For devices with the external memory interface, it is
possible to execute a table read from an external
program memory space and read the contents of the
on-chip memory. An additional code protection bit,
EBTR (CONFIG7L<0>), is used to protect the on-chip
program memory space from this possibility. Setting
EBTR prevents table read commands from executing
on any address in the on-chip program memory space.
EBTR is implemented only on devices with the external
memory interface. Its operation also depends on the
particular mode of operation selected. In Extended
Microcontroller mode, programming EBTR enables
protection from external table reads for the entire
program memory. In Microcontroller with Boot Block
mode, only the first 2 Kbytes of on-chip memory (000h
to 7FFh) are protected. This is because, only this range
of internal program memory is accessible by the
microcontroller in this operating mode.
When the device is in Micrcontroller or Microprocessor
modes, EBTR has no effect on code protection.
24.5.2 CONFIGURATION REGISTER
PROTECTION
The Configuration registers can only be written via
ICSP using an external programmer. No separate
protection bit is associated with them.
FIGURE 24-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6310/6410/8310/8410
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L
— — — — — — —CP
30000Ch CONFIG7L*
— — — — — — — EBTR
Legend: Shaded cells are unimplemented.
* Unimplemented in PIC18F6310/8310 devices; maintain this bit set.
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
8Kbytes
(PIC18F6310/8310)
Address
Range
16 Kbytes
(PIC18F6410/8410)
Address
Range
Program memory
Block
000000h
001FFFh
Program memory
Block
000000h
003FFFh
CP, EBTR
Unimplemented
Read ‘0’s
002000h
1FFFFFh
Unimplemented
Read ‘0’s
004000h
1FFFFFh
(Unimplemented Memory Space)