Datasheet

 2010 Microchip Technology Inc. DS39635C-page 249
PIC18F6310/6410/8310/8410
FIGURE 19-5: ASYNCHRONOUS RECEPTION
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63
PIR3 — — RC2IF TX2IF — — — CCP3IF 65
PIE3 — — RC2IE TX2IE — — — CCP3IE 65
IPR3
— — RC2IP TX2IP — — — CCP3IP 65
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66
RCREG2 AUSART2 Receive Register 66
TXSTA2
CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 66
SPBRG2 AUSART2 Baud Rate Generator Register 66
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit bit 7/8bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bitbit 7/8 Stop
bit
RX2 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG2
Word 2
RCREG2
Stop
bit
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer 2) is read after the third word,
causing the OERR (Overrun) bit to be set.