Datasheet

 2010 Microchip Technology Inc. DS39635C-page 239
PIC18F6310/6410/8310/8410
18.4 EUSART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
18.4.1 EUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG1 and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG1
register.
c) Flag bit, TX1IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e) If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by set-
ting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXIE.
4. If the signal from the CKx pin is to be inverted,
set the TXCKP bit.
5. If 9-bit transmission is desired, set bit, TX9.
6. Enable the transmission by setting enable bit,
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
8. Start transmission by loading data to the
TXREGx register.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63
PIR1
PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65
PIE1
PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65
IPR1
PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65
TXREG1 EUSART1 Transmit Register 65
TXSTA1 CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 65
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.