Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 238  2010 Microchip Technology Inc.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63
PIR1
PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65
PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65
IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65
RCSTA1 SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 65
RCREG1 EUSART1 Receive Register 65
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.