Datasheet

 2010 Microchip Technology Inc. DS39635C-page 235
PIC18F6310/6410/8310/8410
18.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA1<7>), is set in order to configure the TX1 and
RX1 pins to CK1 (clock) and DT1 (data) lines,
respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK1 line. Clock polarity
(CK1) is selected with the TXCKP bit (BAUDCON<4>).
Setting TXCKP sets the Idle state on CK1 as high,
while clearing the bit sets the Idle state as low.
18.3.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG1 register (if available).
Once the TXREG1 register transfers the data to the
TSR register (occurs in one T
CYCLE), the TXREG1 is
empty and the TX1IF flag bit (PIR1<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is
set regardless of the state of enable bit, TX1IE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG1 register.
While flag bit, TX1IF, indicates the status of the TXREG1
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud
rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If the signal from the CKx pin is to be inverted,
set the TXCKP bit.
4. If interrupts are desired, set enable bit, TXIE.
5. If 9-bit transmission is desired, set bit, TX9.
6. Enable the transmission by setting bit, TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
8. Start transmission by loading data to the TXREG
register.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-11: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX1/DT1
RC6/TX1/CK1 pin
Write to
TXREG1 Reg
TX1IF bit
(Interrupt Flag)
TXEN bit
‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG1 = 0, continuous transmission of two 8-bit words.
pin
RC6/TX1/CK1 pin
(TXCKP = 0)
(TXCKP = 1)