Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 230  2010 Microchip Technology Inc.
FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM
FIGURE 18-7: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
Baud Rate Generator
RX1
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR FERR
RSR Register
MSb
LSb
RX9D RCREG1 Register
FIFO
Interrupt
RC1IF
RC1IE
Data Bus
8
 64
 16
or
Stop
Start
(8) 7 1 0
RX9

SPBRG1SPBRGH1
BRG16
or
 4
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX1 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG1
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Word 1
RCREG1
Word 2
RCREG1
Stop
bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer) is read after the third word causing
the OERR (Overrun) bit to be set.