Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 186  2010 Microchip Technology Inc.
17.4 I
2
C Mode
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs through
the TRISC<4:3> bits.
FIGURE 17-7: MSSP BLOCK DIAGRAM
(I
2
C™ MODE)
17.4.1 REGISTERS
The MSSP module has six registers for I
2
C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I
2
C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper 2 bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to, or read from.
SSPADD register holds the slave device address
when the MSSP is configured in I
2
C Slave mode.
When the MSSP is configured in Master mode, the
lower 7 bits of SSPADD act as the Baud Rate
Generator reload value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
SCL
SDA
Shift
Clock
MSb
LSb