Datasheet

 2010 Microchip Technology Inc. DS39635C-page 169
PIC18F6310/6410/8310/8410
16.2 Capture Mode
In Capture mode, the CCPR2H:CCPR2L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the CCP2 pin (RC1
or RE7, depending on device configuration). An event
is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP2M<3:0> (CCP2CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP2IF (PIR2<1>),
is set; it must be cleared in software. If another capture
occurs before the value in register CCPR2 is read, the
old captured value is overwritten by the new captured
value.
16.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
16.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 16.1.1 “CCP Modules and Timer
Resources”).
FIGURE 16-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RC1/CCP2 or RE7/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 Pin
Prescaler
 1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H
CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 Pin
Prescaler
 1, 4, 16
TMR3H TMR3L
TMR1
Enable
TMR3H TMR3L
and
Edge Detect
4
4
4
Q1:Q4
CCPR3H
CCPR3L
TMR1H TMR1L
Set CCP3IF
TMR3
Enable
CCP3CON<3:0>
CCP3 Pin
Prescaler
 1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
and
Edge Detect
4
4
T3CCP1
T3CCP1