Datasheet

 2010 Microchip Technology Inc. DS39635C-page 105
PIC18F6310/6410/8310/8410
8.4 Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory
operations.
If operations in a lower power Run mode are antici-
pated, users should provide in their applications for
adjusting memory access times at the lower clock
speeds.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are sus-
pended. The state of the external bus is frozen with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins which are held at logic high.
TABLE 8-2: REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY INTERFACE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
MEMCON EBDIS
—WAIT1WAIT0 — —
WM1 WM0
65
CONFIG3L WAIT BW
— — — —PM1PM0285
CONFIG3H MCLRE — — — — LPT1OSC — CCP2MX 286
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the external memory interface.