Datasheet

PIC18F47J53 FAMILY
DS39964B-page 550 Preliminary  2010 Microchip Technology Inc.
FIGURE 31-20: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 31-28: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 31-21: EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 31-29: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV Sync XMIT (Master and Slave)
Clock High to Data Out Valid — 40 ns
121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 TDTRF Data Out Rise Time and Fall Time — 20 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL Sync RCV (Master and Slave)
Data Hold before CKx  (DTx hold time) 10 — ns
126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns
121
121
120
122
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 31-4 for load conditions.
125
126
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 31-4 for load conditions.