Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 543
PIC18F47J53 FAMILY
FIGURE 31-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 31-21: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 35 — ns V
DD = 3.3V,
V
DDCORE = 2.5V
100 — ns V
DD = 2.15V,
V
DDCORE = 2.15V
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 30 — ns V
DD = 3.3V,
V
DDCORE = 2.5V
83 — ns VDD = 2.15V
75 TDOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC
76 T
DOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC
78 T
SCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC
81 T
DOV2SCH,
T
DOV2SCL
SDOx Data Output Setup to SCKx Edge T
CY —ns
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
81
74
75, 76
78
MSb
79
73
MSb In
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 31-4 for load conditions.