Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 541
PIC18F47J53 FAMILY
TABLE 31-18: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
FIGURE 31-11: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TABLE 31-19: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Param.
No
Symbol Characteristics Min Typ Max Units
PM1 PMALL/PMALH Pulse Width — 0.5 T
CY —ns
PM2 Address Out Valid to PMALL/PMALH
Invalid (address setup time)
— 0.75 TCY —ns
PM3 PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
— 0.25 T
CY —ns
PM5 PMRD Pulse Width — 0.5 T
CY —ns
PM6 PMRD or PMENB Active to Data In Valid
(data setup time)
———ns
PM7 PMRD or PMENB Inactive to Data In Invalid
(data hold time)
———ns
Param.
No
Symbol Characteristics Min Typ Max Units
PM11 PMWR Pulse Width — 0.5 T
CY —ns
PM12 Data Out Valid before PMWR or PMENB
goes Inactive (data setup time)
———ns
PM13 PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
———ns
PM16 PMCS Pulse Width T
CY – 5 — — ns
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
System
PMALL/
PMD<7:0>
Address
PMA<13:18>
PMWR
PMCS<2:1>
PMRD
Clock
PM12
PM13
PM11
PM16
Data
Address<7:0>
PMALH
Note: Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.