Datasheet

PIC18F47J53 FAMILY
DS39964B-page 36 Preliminary  2010 Microchip Technology Inc.
FIGURE 3-1: PIC18F47J53 FAMILY CLOCK DIAGRAM
OSC1
OSC2
Primary Oscillator
CPU
Peripherals
IDLE
INTOSC Postscaler
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
111
110
101
100
011
010
001
000
31 kHz
INTRC
31 kHz
Internal
Oscillator
Block
8 MHz
8 MHz
0
1
OSCTUNE<7>
PLLDIV<2:0>
CPU Divider
 1
 2
 3
 6
USB Module
4 MHz
WDT, PWRT, FSCM
and Two-Speed Start-up
OSCCON<6:4>
PLLEN
1
0
F
OSC2
1
0
PLL Prescaler
96 MHz
PLL
(1)
 2
1
0
FSEN
 8
1
0
 4
LS48MHZ
00
01
10
11
CPDIV<1:0>
(Note 2)
00
FOSC<2:1>
Other
00
01
OSCCON<1:0>
11
 4
RA6
CLKO
Enabled Modes
Timer1 Clock
(3)
Postscaled
Internal Clock
T1OSI
T1OSO
Secondary Oscillator
Clock
Needs 48 MHz for FS
Needs 6 MHz for LS
Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit
in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to t
rc
to lock. During this time, the
device continues to be clocked at the PLL bypassed frequency.
2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this
node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.
3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 3.6 “Reference Clock Output”) and PLL.
4: The USB module cannot be used to communicate unless the primary clock source is selected.
 12
 10
 6
 5
 4
 3
 2
 1
000
001
010
011
100
101
110
111
48 MHz
Primary Clock
Source
(4)
CFGPLLEN