Datasheet
PIC18F47J53 FAMILY
DS39964B-page 150 Preliminary 2010 Microchip Technology Inc.
RB4/CCP4/
PMA1/KBI0/
SCK1/SCL1/
RP7
RB4 0 O DIG LATB<4> data output; not affected by analog input.
1 I TTL PORTB<4> data input; weak pull-up when the RBPU
bit is
cleared. Disabled when analog input is enabled.
(1)
CCP4
(3)
1
I ST Capture input.
0
O DIG Compare/PWM output.
PMA1 x I/O ST/TTL/
DIG
Parallel Master Port address.
KBI0 1 I TTL Interrupt-on-change pin.
SCK1 1 I ST Parallel Master Port io_addr_in<1>.
0 O DIG Parallel Master Port address.
SCL1 1 II
2
C/
SMBus
I
2
C™ clock input (MSSP1 module).
0 ODIGI
2
C clock output (MSSP1 module).
RP7 1 I ST Remappable Peripheral Pin 7 input.
0 O DIG Remappable Peripheral Pin 7 output.
RB5/CCP5/
PMA0/KBI1/
SDI1/SDA1/
RP8
RB5 0 O DIG LATB<5> data output.
1 I TTL PORTB<5> data input; weak pull-up when the RBPU
bit is
cleared.
CCP5
(3)
1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA0
(3)
x I/O ST/TTL/
DIG
Parallel Master Port address.
KBI1 1 I TTL Interrupt-on-change pin.
SDI1 1 I ST SPI data input (MSSP1 module).
SDA1 1 II
2
C/
SMBus
I
2
C data input (MSSP1 module).
0 ODIGI
2
C/SMBus.
RP8 1 I ST Remappable Peripheral Pin 8 input.
0 O DIG Remappable Peripheral Pin 8 output.
RB6/CCP6/
KBI2/PGC/RP9
RB6 0 O DIG LATB<6> data output.
1 I TTL PORTB<6> data input; weak pull-up when the RBPU
bit is
cleared.
CCP6
(3)
1
I ST Capture input.
0 O DIG Compare/PWM output.
KBI2 1 I TTL Interrupt-on-change pin.
PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD
operation.
(2)
RP9 1 I ST Remappable Peripheral Pin 9 input.
0 O DIG Remappable Peripheral Pin 9 output.
TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
3: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).