Datasheet

PIC18F47J13 FAMILY
DS39974A-page 546 Preliminary  2010 Microchip Technology Inc.
Extended Instruction Set
ADDFSR .................................................................. 476
ADDULNK ................................................................ 476
CALLW .....................................................................477
MOVSF ....................................................................477
MOVSS .................................................................... 478
PUSHL .....................................................................478
SUBFSR ................................................................... 479
SUBULNK ................................................................479
External Clock Input ........................................................... 38
F
Fail-Safe Clock Monitor ............................................ 415, 428
Interrupts in Power-Managed Modes ....................... 430
POR or Wake-up From Sleep .................................. 430
WDT During Oscillator Failure ................................. 429
Fast Register Stack (FSR) .................................................85
Firmware Instructions ....................................................... 433
Flash Program Memory
Write Sequence ........................................................ 115
Flash Program Memory .................................................... 107
Associated Registers ...............................................116
Control Registers .....................................................108
EECON1 and EECON2 ...................................108
TABLAT (Table Latch) Register ....................... 110
TBLPTR (Table Pointer) Register .................... 110
Erase Sequence ....................................................... 112
Erasing ..................................................................... 112
Operation During Code-Protect ................................116
Reading ....................................................................111
Table Pointer
Boundaries Based on Operation ...................... 110
Table Pointer Boundaries .........................................110
Table Reads and Table Writes .................................107
Write Sequence ........................................................ 113
Writing ......................................................................113
Unexpected Termination .................................. 116
Write Verify ...................................................... 116
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 454
H
Hardware Multiplier .......................................................... 117
8 x 8 Multiplication Algorithms .................................. 117
Operation ................................................................. 117
Performance Comparison (table) .............................117
High/Low-Voltage Detect .................................................391
Applications .............................................................. 395
Associated Registers ...............................................396
Characteristics .........................................................505
Current Consumption ...............................................393
Effects of a Reset ..................................................... 396
Operation ................................................................. 392
During Sleep .................................................... 396
Setup ........................................................................ 393
Start-up Time ...........................................................393
Typical Application ................................................... 395
I
I/O Ports ........................................................................... 139
Open-Drain Outputs .................................................140
Pin Capabilities ........................................................ 139
TTL Input Buffer Option ............................................ 140
I
2
C Mode .......................................................................... 310
I
2
C Mode (MSSP)
Acknowledge Sequence Timing .............................. 338
Associated Registers ............................................... 344
Baud Rate Generator ............................................... 331
Bus Collision
During a Repeated Start Condition .................. 342
During a Stop Condition ................................... 343
Clock Arbitration ...................................................... 333
Clock Stretching ....................................................... 325
10-Bit Slave Receive Mode (SEN = 1) ............ 325
10-Bit Slave Transmit Mode ............................ 325
7-Bit Slave Receive Mode (SEN = 1) .............. 325
7-Bit Slave Transmit Mode .............................. 325
Clock Synchronization and CKP bit ......................... 326
Effects of a Reset .................................................... 339
General Call Address Support ................................. 329
I
2
C Clock Rate w/BRG ............................................. 332
Master Mode ............................................................ 329
Operation ......................................................... 331
Reception ........................................................ 335
Repeated Start Condition Timing ..................... 334
Start Condition Timing ..................................... 333
Transmission ................................................... 335
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 339
Multi-Master Mode ................................................... 339
Operation ................................................................. 315
Read/Write
Bit Information (R/W Bit) ................315, 318
Registers .................................................................. 310
Serial Clock (SCLx Pin) ........................................... 318
Slave Mode .............................................................. 315
Addressing ....................................................... 315
Addressing Masking Modes
5-Bit ......................................................... 316
7-Bit ......................................................... 317
Reception ........................................................ 318
Transmission ................................................... 318
Sleep Operation ....................................................... 339
Stop Condition Timing ............................................. 338
INCF ................................................................................ 454
INCFSZ ............................................................................ 455
In-Circuit Debugger .......................................................... 431
In-Circuit Serial Programming (ICSP) .......................415, 431
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 480
Indexed Literal Offset Mode ............................................. 480
Indirect Addressing .......................................................... 102
INFSNZ ............................................................................ 455
Initialization Conditions for All Registers .......................71–79
Instruction Cycle ................................................................ 86
Clocking Scheme ....................................................... 86
Flow/Pipelining ........................................................... 86
Instruction Set .................................................................. 433
ADDLW .................................................................... 439
ADDWF .................................................................... 439
ADDWF (Indexed Literal Offset Mode) .................... 481
ADDWFC ................................................................. 440
ANDLW .................................................................... 440
ANDWF .................................................................... 441
BC ............................................................................ 441
BCF .......................................................................... 442
BN ............................................................................ 442
BNC ......................................................................... 443
BNN ......................................................................... 443