Datasheet

PIC18F47J13 FAMILY
DS39974A-page 528 Preliminary 2010 Microchip Technology Inc.
TABLE 30-32: 10-BIT A/D CONVERSION REQUIREMENTS
TABLE 30-33: 12-BIT A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period 0.7 25.0
(1)
sTOSC based, VREF 3.0V
131 TCNV Conversion Time
(not including acquisition time)
(2)
11 12 TAD
132 TACQ Acquisition Time
(3)
1.4 s-40C to +85C
135 TSWC Switching Time from Convert Sample (Note 4)
137 T
DIS Discharge Time 0.2 s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following T
CY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50W.
4: On the following cycle of the device clock.
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period 0.8 12.5
(1)
sTOSC based, VREF 3.0V
131 T
CNV Conversion Time
(not including acquisition time)
(2)
13 14 TAD
132 TACQ Acquisition Time
(3)
1.4 s
135 T
SWC Switching Time from Convert Sample (Note 4)
137 TDIS Discharge Time 0.2 s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.