Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 333
PIC18F47J13 FAMILY
20.5.7.2 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the BRG is
suspended from counting until the SCLx pin is actually
sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of SSPxADD<6:0>
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device (Figure 20-20).
FIGURE 20-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
20.5.8 I
2
C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the BRG is reloaded with
the contents of SSPxADD<6:0> and starts its count. If
SCLx and SDAx are both sampled high when the Baud
Rate Generator times out (T
BRG), the SDAx pin is
driven low. The action of the SDAx being driven low
while SCLx is high is the Start condition and causes the
Start bit (SSPxSTAT<3>) to be set. Following this, the
BRG is reloaded with the contents of SSPxADD<6:0>
and resumes its count. When the BRG times out
(T
BRG), the SEN bit (SSPxCON2<0>) will be
automatically cleared by hardware. The BRG is
suspended, leaving the SDAx line held low and the Start
condition is complete.
20.5.8.1 WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write does not occur).
FIGURE 20-21: FIRST START BIT TIMING
SDAx
SCLx
SCLx Deasserted but Slave Holds
DX – 1DX
BRG
SCLx is Sampled High, Reload takes
place and BRG Starts its Count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCLx Low (clock arbitration)
SCLx Allowed to Transition High
BRG Decrements on
Q2 and Q4 Cycles
Note: If, at the beginning of the Start condition, the
SDAx and SCLx pins are already sampled
low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLxIF, is
set, the Start condition is aborted and the
I
2
C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.
SDAx
SCLx
S
TBRG
1st bit
2nd bit
TBRG
SDAx = 1,
At Completion of Start bit,
SCLx = 1
Write to SSPxBUF Occurs Here
TBRG
Hardware Clears SEN bit
TBRG
Write to SEN bit Occurs Here
Set S bit (SSPxSTAT<3>)
and Sets SSPxIF bit