Datasheet

PIC18F66K80 FAMILY
DS39977F-page 500  2010-2012 Microchip Technology Inc.
COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0
 f  255
d
 [0,1]
a
 [0,1]
Operation: f
 dest
Status Affected: N, Z
Encoding:
0001 11da ffff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘
0’, the result is
stored in W. If ‘d’ is ‘
1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘
0’, the Access Bank is selected.
If ‘a’ is ‘
1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example:
COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W=ECh
CPFSEQ Compare f with W, Skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0
 f  255
a
 [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding:
0110 001a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W
, then the fetched instruction is
discarded and a
NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘
0’, the Access Bank is selected.
If ‘a’ is ‘
1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address =
HERE
W=?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG  W;
PC = Address
(NEQUAL)