Datasheet

PIC18F2XK20/4XK20
DS41303G-page 452  2010 Microchip Technology Inc.
A/D Conversion Requirements ................................402
Capture/Compare/PWM Requirements ................... 390
CLKO and I/O Requirements ...................................387
Example SPI Mode Requirements
(Master Mode, CKE = 0) ..................................392
(Master Mode, CKE = 1) ..................................393
(Slave Mode, CKE = 0) ....................................394
(Slave Mode, CKE = 1) ....................................395
External Clock Requirements ..................................385
I
2
C Bus Data Requirements (Slave Mode) .............. 397
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ....................................................396
Master SSP I
2
C Bus Data Requirements ................399
Master SSP I
2
C Bus Start/Stop Bits
Requirements ...................................................398
Parallel Slave Port Requirements (PIC18F4X20) .... 391
PLL Clock .................................................................386
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ...................................................388
Timer0 and Timer1 External Clock Requirements ...389
USART Synchronous Receive Requirements .........400
USART Synchronous Transmission
Requirements ...................................................400
Top-of-Stack Access ..........................................................66
TRISE Register ................................................................134
PSPMODE Bit ..........................................................130
TSTFSZ ............................................................................355
Two-Speed Clock Start-up Mode ....................................... 38
Two-Speed Start-up .........................................................299
Two-Word Instructions
Example Cases ..........................................................70
TXREG .............................................................................239
TXSTA Register ...............................................................246
BRGH Bit .................................................................249
V
Voltage Reference (VR)
Specifications ...........................................................381
Voltage Reference. See Comparator Voltage
Reference (CV
REF)
Voltage References
Fixed Voltage Reference (FVR) ............................... 290
VR Stabilization ........................................................290
V
REF. SEE ADC Reference Voltage
W
Wake-up on Break ...........................................................254
Watchdog Timer (WDT) ...........................................299, 308
Associated Registers ...............................................309
Control Register .......................................................309
Programming Considerations ..................................308
WCOL ......................................................223, 224, 225, 228
WCOL Status Flag ...................................223, 224, 225, 228
WDTCON Register ...........................................................309
WWW Address .................................................................453
WWW, On-Line Support .....................................................10
X
XORLW ............................................................................355
XORWF ............................................................................356