Datasheet

 2010 Microchip Technology Inc. DS41303G-page 215

PIC18F2XK20/4XK20

17.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already sam-

pled low. Therefore, the CKP bit will not assert the

SCL line until an external I

C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I

C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 17-12).

FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON1

CKP

Master device

deasserts clock

Master device

asserts clock