Datasheet

 2010 Microchip Technology Inc. DS41303G-page 191
PIC18F2XK20/4XK20
TABLE 16-2: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
RCON IPEN
SBOREN — RI TO PD POR BOR 58
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 62
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 62
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 62
PIR2
OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 62
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 62
IPR2
OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 62
TRISB PORTB Data Direction Control Register 62
TRISC PORTC Data Direction Control Register 62
TRISD PORTD Data Direction Control Register 62
TMR1L Timer1 Register, Low Byte 60
TMR1H Timer1 Register, High Byte 60
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 60
TMR2 Timer2 Register 60
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 60
PR2 Timer2 Period Register 60
TMR3L Timer3 Register, Low Byte 61
TMR3H Timer3 Register, High Byte 61
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 61
CCPR1L Capture/Compare/PWM Register 1, Low Byte 61
CCPR1H Capture/Compare/PWM Register 1, High Byte 61
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 61
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.