Datasheet

PIC18F2XK20/4XK20
DS41303G-page 150  2010 Microchip Technology Inc.
11.4.1 PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1: PWM PERIOD
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPR
xL into
CCPR
xH.
11.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR
xL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPR
xL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 11-2: PULSE WIDTH
EQUATION 11-3: DUTY CYCLE RATIO
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
OSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR
xH and
2-bit latch, then the CCPx pin is cleared (see
Figure 11-3).
Note: The Timer2 postscaler (see Section 14.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
PWM Period PR21+4TOSC =
(TMR2 Prescale Value)
Note: T
OSC = 1/FOSC.
Pulse Width CCPRxL:DCxB<1:0>  =
T
OSC  (TMR2 Prescale Value)
Duty Cycle Ratio
CCPRxL:DCxB<1:0>
4PR2 1+
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