Datasheet

 2010 Microchip Technology Inc. DS41303G-page 129
PIC18F2XK20/4XK20
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 62
LATC PORTC Data Latch Register (Read and Write to Data Latch) 62
TRISC PORTC Data Direction Control Register 62
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 60
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 61
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 61
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 61
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 60
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 61
ECCP1AS
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 61
SLRCON — — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: Not implemented on PIC18F2XK20 devices.