Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 569
PIC18F47J53 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (December 2009)
Original data sheet for PIC18F47J53 family devices.
Revision B (June 2010)
Updates typical and maximum DC current specifica-
tions in Section 31.2 “DC Characteristics:
Power-Down and Supply Current PIC18F47J53
Family (Industrial)”.
Removes all references to the LPT1OSC Configuration
bit throughout the data sheet; substitutes appropriate
references to the SOSCSEL Configuration bits.
APPENDIX B: MIGRATION FROM
PIC18F46J50 TO
PIC18F47J53
Code for the devices in the PIC18F46J50 family can be
migrated to the PIC18F47J53 without many changes.
The differences between the two device families are
listed in Table B-1.
TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F47J53 AND PIC18F46J50 FAMILIES
Characteristic
PIC18F47J53 Family PIC18F46J50 Family
Max Program Memory 128 Kbytes 64 Kbytes
Oscillator options PLL can be enabled at start-up with
Config bit option
Requires firmware to set the PLLEN bit at
run time
SOSC Oscillator Options Low-power oscillator option for SOSC,
with run-time switch
Low-power oscillator option for SOSC,
only via Configuration bit setting
T1CKI Clock Input T1CKI can be used as a clock input
without enabling the Timer1 oscillator
No
INTOSC Up to 8 MHz Up to 8 MHz
Timers 8 5
ECCP 3 2
CCP 7 0
SPI Fosc/8 Master Clock
Option
Yes No
ADC 13 Channel, 10/12-bit conversion modes
with Special Event Trigger option.
13 Channel, 10-bit only
Peripheral Module Disable
Bits
Yes, allowing further power reduction No
Band Gap Voltage Reference
Output
Yes, enabled on pin RA1 by setting the
VBGOE bit (WDTCON<4>)
No
REPU/RDPU Pull-Up Enable
Bits
Moved to TRISE register (avoids read,
modify, write issues)
Pull-up bits configured in PORTE register
Comparators Three, each with four input-pin selections Two, each with two input-pin selections
Increased Output Drive
Strength
RA0 through RA5, RDx and REx No