Datasheet

PIC18F46J50 FAMILY
DS39931D-page 94  2011 Microchip Technology Inc.
ANCON1 VBGEN r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 00-0 0000 74, 348
ANCON0 PCFG7
(5)
PCFG6
(5)
PCFG5
(5)
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 74, 347
ODCON1
— — — — — — ECCP20D ECCP10D ---- --00 74, 134
ODCON2
— — — — — — U2OD U1OD ---- --00 74, 134
ODCON3
— — — — — — SPI2OD SPI1OD ---- --00 74, 135
RTCCFG RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000 74, 227
RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000 74, 228
REFOCON ROON
— ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 74, 44
PADCFG1
— — — — — RTSECSEL1 RTSECSEL0 PMPTTL ---- -000 74, 135
UCFG UTEYE UOEMON
— UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 74, 360
UADDR
— ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 74, 365
UEIE BTSEE
— — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 74, 377
UIE
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 74, 375
UEP15
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP14
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP13
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP12
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP11
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP10
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP9
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP8
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP7
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
UEP6
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP5
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP4
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP3
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP2
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP1
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
UEP0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
PPSCON
— — — — — — —IOLOCK---- ---0 155
RPINR24
— — — Input Function FLT0 to Input Pin Mapping Bits ---1 1111 75, 160
RPINR23
— — — Input Function SS2 to Input Pin Mapping Bits ---1 1111
75, 160
RPINR22
— — — Input Function SCK2 to Input Pin Mapping Bits ---1 1111 75, 160
RPINR21
— — — Input Function SDI2 to Input Pin Mapping Bits ---1 1111 75, 159
RPINR17
— — — Input Function CK2 to Input Pin Mapping Bits ---1 1111 75, 159
RPINR16
— — — Input Function RX2DT2 to Input Pin Mapping Bits ---1 1111 75
RPINR13
— — — Input Function T3G to Input Pin Mapping Bits ---1 1111 75
RPINR12
— — — Input Function T1G to Input Pin Mapping Bits ---1 1111 75, 158
RPINR8
— — — Input Function IC2 to Input Pin Mapping Bits ---1 1111 75, 158
RPINR7
— — — Input Function IC1 to Input Pin Mapping Bits ---1 1111 75, 157
RPINR6
— — — Input Function T3CKI to Input Pin Mapping Bits ---1 1111 75, 157
RPINR4
— — — Input Function T0CKI to Input Pin Mapping Bits ---1 1111 75, 157
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7: The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.