Datasheet
2011 Microchip Technology Inc. DS39931D-page 93
PIC18F46J50 FAMILY
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 270,
322
GCEN ACKSTAT ADMSK5
(4)
ADMSK4
(4)
ADMSK3
(4)
ADMSK2
(4)
ADMSK1
(4)
SEN
CMSTAT
— — — — — — COUT2 COUT1 ---- --11 73, 389
PMADDRH/
— CS1 Parallel Master Port Address High Byte -000 0000 73, 177
PMDOUT1H
(5,6)
Parallel Port Out Data High Byte (Buffer 1) 0000 0000 73, 180
PMADDRL/ Parallel Master Port Address Low Byte 0000 0000 73, 176
PMDOUT1L
(5,6)
Parallel Port Out Data Low Byte (Buffer 0) 0000 0000 73, 177
PMDIN1H
(5)
Parallel Port In Data High Byte (Buffer 1) 0000 0000 73, 177
PMDIN1L
(5)
Parallel Port In Data Low Byte (Buffer 0) 0000 0000 73, 177
TXADDRL SPI DMA Transit Data Pointer Low Byte xxxx xxxx 73, 284
TXADDRH
— — — — SPI DMA Transit Data Pointer High Byte ---- xxxx 73, 284
RXADDRL SPI DMA Receive Data Pointer Low Byte xxxx xxxx 73, 284
RXADDRH
— — — — SPI DMA Receive Data Pointer High Byte ---- xxxx 73, 284
DMABCL SPI DMA Byte Count Low Byte xxxx xxxx 73, 284
DMABCH
— — — — — — SPI DMA Byte Count High
Byte
---- --xx 73, 284
UCON
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 73, 359
USTAT
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 73, 363
UEIR BTSEF
— — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 73, 376
UIR
— SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 73, 373
UFRMH
— — — — —FRM10FRM9FRM8---- -xxx 73, 365
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 73, 365
PMCONH
(5)
PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0--0 0000 73, 170
PMCONL
(5)
CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 000- 0000 73, 171
PMMODEH
(5)
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000 74, 172
PMMODEL
(5)
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000 74, 173
PMDOUT2H
(5)
Parallel Port Out Data High Byte (Buffer 3) 0000 0000 74, 176
PMDOUT2L
(5)
Parallel Port Out Data Low Byte (Buffer 2) 0000 0000 74, 176
PMDIN2H
(5)
Parallel Port In Data High Byte (Buffer 3) 0000 0000 74, 176
PMDIN2L
(5)
Parallel Port In Data Low Byte (Buffer 2) 0000 0000 74, 176
PMEH
(5)
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000 74, 174
PMEL
(5)
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000 74, 174
PMSTATH
(5)
IBF IBOV — — IB3F IB2F IB1F IB0F 00-- 0000 74, 175
PMSTATL
(5)
OBE OBUF — — OB3E OB2E OB1E OB0E 10-- 1111 74, 175
CVRCON CVREN CVROE CVRR
r CVR3 CVR2 CVR1 CVR0 0000 0000 74, 392
TCLKCON
— — —T1RUN — — T3CCP2 T3CCP1 ---0 --00 202
DSGPR1 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 58
DSGPR0 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 58
DSCONH DSEN
— — — — r DSULPEN RTCWDIS 0--- -000 57
DSCONL
— — — — — ULPWDIS DSBOR RELEASE ---- -000 57
DSWAKEH
— — — — — — —DSINT0---- ---0 59
DSWAKEL DSFLT
— DSULP DSWDT DSRTC DSMCLR — DSPOR 0-00 00-1 59
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7: The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.