Datasheet
2011 Microchip Technology Inc. DS39931D-page 91
PIC18F46J50 FAMILY
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 71
CCPR1H Capture/Compare/PWM Register 1 HIgh Byte xxxx xxxx 71
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 71
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 71
PSTR2CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001 71, 265
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 71
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 71
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 71
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 71
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 71
CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN — 0-00 000- 71
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 00xx 71
CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000 71
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 71, 327
RCREG1 EUSART1 Receive Register 0000 0000 71, 336,
328
TXREG1 EUSART1 Transmit Register xxxx xxxx 71, 336,
335
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 333
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 71, 336
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 71, 327
RCREG2 EUSART2 Receive Register 0000 0000 71, 336,
338
TXREG2 EUSART2 Transmit Register 0000 0000 71, 333,
335
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 333
EECON2 Program Memory Control Register 2 (not a physical register) ---- ---- 71, 104
EECON1
— — WPROG FREE WRERR WREN WR — --00 x00- 71, 104
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 1111 1111 71, 126
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 0000 0000 71, 120
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 0000 0000 71, 123
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111 71, 126
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000 71, 120
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000 71, 123
IPR1 PMPIP
(5)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 126
PIR1 PMPIF
(5)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 120
PIE1 PMPIE
(5)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 123
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 72, 336
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 72, 39
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
T1DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 201
RTCVALH RTCC Value Register Window High Byte, Based on RTCPTR<1:0> 0xxx xxxx 72, 231
RTCVALL RTCC Value Register Window Low Byte, Based on RTCPTR<1:0> 0xxx xxxx 72, 231
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7: The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.