Datasheet
PIC18F46J50 FAMILY
DS39931D-page 90 2011 Microchip Technology Inc.
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 69, 98
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 69, 98
BSR
— — — — Bank Select Register ---- 0000 69, 84
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 69, 98
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 70, 99
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 70, 99
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 70, 99
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 70, 99
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 70, 98
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 70, 98
STATUS
— — —N OV Z DCC---x xxxx 70, 96
TMR0H Timer0 Register High Byte 0000 0000 70, 203
TMR0L Timer0 Register Low Byte xxxx xxxx 70, 203
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 70, 196
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS
(2)
— SCS1 SCS0 0110 q-00 70, 43
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 391
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 70, 391
RCON IPEN
—CMRI TO PD POR BOR 0-11 1100 68, 70,
129
TMR1H Timer1 Register High Byte xxxx xxxx 70, 203
TMR1L Timer1 Register Low Byte xxxx xxxx 70, 203
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16 TMR1ON 0000 0000 70, 203
TMR2 Timer2 Register 0000 0000 70, 211
PR2 Timer2 Period Register 1111 1111 70, 211
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 70, 211
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 70, 288,
322
SSP1ADD MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 70, 293
SSP1MSK
(4)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 70, 295
SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 70, 270,
289
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 270,
290
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 70, 270,
291
GCEN ACKSTAT ADMSK5
(4)
ADMSK4
(4)
ADMSK3
(4)
ADMSK2
(4)
ADMSK1
(4)
SEN
ADRESH A/D Result Register High Byte xxxx xxxx 70, 356
ADRESL A/D Result Register Low Byte xxxx xxxx 70, 356
ADCON0 VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE
ADON 0000 0000 69, 347
ADCON1 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 70, 347
WDTCON REGSLP LVDSTAT ULPLVL
— DS ULPEN ULPSINK SWDTEN 1qx- q000 70, 427
PSTR1CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001 70, 265
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7: The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.