Datasheet

 2011 Microchip Technology Inc. DS39931D-page 71
PIC18F46J50 FAMILY
PSTR1CON PIC18F2XJ50 PIC18F4XJ50 00-0 0001 00-0 0001 uu-u uuuu
ECCP1AS PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
ECCP1DEL PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
CCPR1H PIC18F2XJ50 PIC18F4XJ50 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F2XJ50 PIC18F4XJ50 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
PSTR2CON PIC18F2XJ50 PIC18F4XJ50 00-0 0001 00-0 0001 uu-u uuuu
ECCP2AS PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
CCPR2H PIC18F2XJ50 PIC18F4XJ50 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L PIC18F2XJ50 PIC18F4XJ50 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
CTMUCONH PIC18F2XJ50 PIC18F4XJ50 0-00 000- 0-00 000- u-uu uuu-
CTMUCONL PIC18F2XJ50 PIC18F4XJ50 0000 00xx 0000 00xx uuuu uuuu
CTMUICON PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
SPBRG1 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
RCREG1 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
TXREG1 PIC18F2XJ50 PIC18F4XJ50 xxxx xxxx 0000 0000 uuuu uuuu
TXSTA1 PIC18F2XJ50 PIC18F4XJ50 0000 0010 0000 0010 uuuu uuuu
RCSTA1 PIC18F2XJ50 PIC18F4XJ50 0000 000x 0000 000x uuuu uuuu
SPBRG2 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
RCREG2 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
TXREG2 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
TXSTA2 PIC18F2XJ50 PIC18F4XJ50 0000 0010 0000 0010 uuuu uuuu
EECON2 PIC18F2XJ50 PIC18F4XJ50 ---- ---- ---- ---- ---- ----
EECON1 PIC18F2XJ50 PIC18F4XJ50 --00 x00- --00 q00- --00 u00-
IPR3 PIC18F2XJ50 PIC18F4XJ50 1111 1111 1111 1111 uuuu uuuu
PIR3 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
(3)
PIE3 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
IPR2 PIC18F2XJ50 PIC18F4XJ50 1111 1111 1111 1111 uuuu uuuu
PIR2 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
(3)
PIE2 PIC18F2XJ50 PIC18F4XJ50 0000 0000 0000 0000 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset,
Wake From Deep
Sleep
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and the GIEH (and GIEL if low priority) bit(s) are set, the TOSU,
TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the
next location in the hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Tabl e 5 - 1 for Reset value for specific condition.
5: Not implemented on PIC18F2XJ50 devices.
6: Not implemented on “LF” devices.