Datasheet

PIC18F46J50 FAMILY
DS39931D-page 502  2011 Microchip Technology Inc.
30.3 DC Characteristics:PIC18F46J50 Family (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A  +85°C for industrial
Param
No.
Symbol Characteristic Min Max Units Conditions
V
IL Input Low Voltage
All I/O ports:
D030 with TTL Buffer
(4)
VSS 0.15 VDD VVDD < 3.3V
D030A with TTL Buffer
(4)
VSS 0.8 V 3.3V < VDD <3.6V
D031 with Schmitt Trigger Buffer V
SS 0.2 VDD V
D031A SDAx/SCLx VSS 0.3 VDD VI
2
C™ enabled
D031B SDAx/SCLx V
SS 0.8 V SMBus enabled
D032 MCLR
VSS 0.2 VDD V
D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes
D033A
D034
OSC1
T1OSI
VSS
VSS
0.2 VDD
0.3
V
V
EC, ECPLL modes
T1OSCEN = 1
VIH Input High Voltage
I/O Ports without 5.5V
Toleran ce:
D040 with TTL Buffer
(4)
0.25 VDD + 0.8V VDD VVDD < 3.3V
D040A with TTL Buffer
(4)
2.0 VDD V3.3V < VDD <3.6V
D041 with Schmitt Trigger Buffer 0.8 VDD VDD V
I/O Ports with 5.5V Tolerance:
(5)
Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V
DxxxA 2.0 5.5 V 3.3V  VDD 3.6V
Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V
D041A SDAx/SCLx 0.7 V
DD 5.5 V I
2
C™ enabled
D041B SDAx/SCLx 2.1 5.5 V SMBus enabled, VDD > 3V
D042 MCLR 0.8 VDD 5.5 V
D043 OSC1 0.7 V
DD VDD V HS, HSPLL modes
D043A
D044
OSC1
T1OSI
0.8 V
DD
1.6
V
DD
VDD
V
V
EC, ECPLL modes
T1OSCEN = 1
I
IL Input Leakage Current
(1,2)
D060 I/O Ports — ±0.2 AV
SS VPIN VDD,
Pin at high-impedance
D061 MCLR
—±0.2A Vss VPIN VDD
D063 OSC1 — ±0.2 A Vss VPIN VDD
IPU Weak Pull-up Current
D070 I
PURB PORTB, PORTD
(3)
and
PORTE
(3)
Weak Pull-up Current
80 400 AV
DD = 3.3V, VPIN = VSS
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
3: Only available on 44-pin devices.
4: When used as general purpose inputs, the RC4 and RC5 thresholds are referenced to V
USB instead of VDD.
5: Refer to Ta b l e 1 0 -2 for pin tolerance levels.