Datasheet

PIC18F46J50 FAMILY
DS39931D-page 322  2011 Microchip Technology Inc.
TABLE 19-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1
PMPIF
(3)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72
PIE1 PMPIE
(3)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72
IPR1
PMPIP
(3)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF HLVDIF TMR3IF CCP2IF 72
PIE2
OSCFIE CM2IE CM1IE USBIE BCL1IE HLVDIE TMR3IE CCP2IE 72
IPR2 OSCFIP CM2IP CM1IP USBIP BCL1IP HLVDIP TMR3IP CCP2IP 72
PIR3 SSP2IF BCL2IF
RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72
IPR3 SSP2IP BCL2IP
RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 72
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 72
SSP1BUF MSSP1 Receive Buffer/Transmit Register 72
SSPxADD MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C Master mode) 70, 73
SSPxMSK
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 70, 73
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70, 73
SSPxCON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 70, 73
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN 70, 73
SSPxSTAT SMP CKE D/A
PSR/WUA BF 70, 73
SSP2BUF MSSP2 Receive Buffer/Transmit Register 73
SSP2ADD MSSP2 Address Register (I
2
C Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 73
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I
2
C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
2
C Slave mode
operations in 7-Bit Masking mode. See Section 19.5.3.4 “7-Bit Address Masking Mode” for more details.
2: Alternate bit definitions for use in I
2
C Slave mode operations only.
3: These bits are only available on 44-pin devices.