Datasheet

PIC18F46J50 FAMILY
DS39931D-page 252  2011 Microchip Technology Inc.
TABLE 18-3: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
RCON IPEN
— CM RI TO PD POR BOR 70
PIR1
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72
IPR2
OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 72
PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 72
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 72
TCLKCON
— — — T1RUN — — T3CCP2 T3CCP1 74
TMR2 Timer2 Register 70
PR2 Timer2 Period Register 70
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70
TMR4 Timer4 Register 73
PR4 Timer4 Period Register 73
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 73
CCPR1L Capture/Compare/PWM Register 1 Low Byte 71
CCPR1H Capture/Compare/PWM Register 1 High Byte 71
CCPRL2L Capture/Compare/PWM Register 2 Low Byte 71
CCPR2H Capture/Compare/PWM Register 2 High Byte 71
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 73
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 73
ODCON1
— — — — — —ECCP2ODECCP1OD74
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.