Datasheet

PIC18F46J50 FAMILY
DS39931D-page 210  2011 Microchip Technology Inc.
FIGURE 13-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TABLE 13-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 89
PIR1
PMPIF
(1)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 91
PIE1 PMPIE
(1)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 91
IPR1
PMPIP
(1)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 91
TMR1L Timer1 Register Low Byte 90
TMR1H Timer1 Register High Byte 90
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16 TMR1ON
90
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
T1DO
NE
T1GVAL T1GSS1 T1GSS0 91
TCLKCON
— — — T1RUN — — T3CCP2 T3CCP1 93
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are only available on 44-pin devices.
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
T1GSPM
T1GGO/
T1DONE
Set by Software
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Hardware on
Falling Edge of T1GVAL
Cleared by Software
Cleared by
Software
TMR1GIF
T1GTM
Counting Enabled on
Rising Edge of T1G
N + 4
N + 3