Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 83
PIC18F2585/2680/4585/4680
B4EIDL
(8)
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 299
B4EIDH
(8)
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 57, 298
B4SIDL
(8)
Receive mode
SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 56, 297
B4SIDL
(8)
Transmit mode
SID2 SID1 SID0 — EXIDE —EID17EID16xxx- x-xx 56, 297
B4SIDH
(8)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 57, 296
B4CON
(8)
Receive mode
RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 57, 294
B4CON
(8)
Transmit mode
TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 57, 295
B3D7
(8)
B3D77 B3D76 B3D75 B3D74 B3D73 B3D72 B3D71 B3D70 xxxx xxxx 57, 299
B3D6
(8)
B3D67 B3D66 B3D65 B3D64 B3D63 B3D62 B3D61 B3D60 xxxx xxxx 57, 299
B3D5
(8)
B3D57 B3D56 B3D55 B3D54 B3D53 B3D52 B3D51 B3D50 xxxx xxxx 57, 299
B3D4
(8)
B3D47 B3D46 B3D45 B3D44 B3D43 B3D42 B3D41 B3D40 xxxx xxxx 57, 299
B3D3
(8)
B3D37 B3D36 B3D35 B3D34 B3D33 B3D32 B3D31 B3D30 xxxx xxxx 57, 299
B3D2
(8)
B3D27 B3D26 B3D25 B3D24 B3D23 B3D22 B3D21 B3D20 xxxx xxxx 57, 299
B3D1
(8)
B3D17 B3D16 B3D15 B3D14 B3D13 B3D12 B3D11 B3D10 xxxx xxxx 57, 299
B3D0
(8)
B3D07 B3D06 B3D05 B3D04 B3D03 B3D02 B3D01 B3D00 xxxx xxxx 57, 299
B3DLC
(8)
Receive mode
— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 300
B3DLC
(8)
Transmit
mode
—TXRTR— — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 301
B3EIDL
(8)
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 57, 299
B3EIDH
(8)
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 57, 298
B3SIDL
(8)
Receive mode
SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 56, 297
B3SIDL
(8)
Transmit mode
SID2 SID1 SID0 — EXIDE —EID17EID16xxx- x-xx 56, 297
B3SIDH
(8)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 57, 296
B3CON
(8)
Receive mode
RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 57, 294
B3CON
(8)
Transmit mode
TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 57, 295
B2D7
(8)
B2D77 B2D76 B2D75 B2D74 B2D73 B2D72 B2D71 B2D70 xxxx xxxx 57, 299
B2D6
(8)
B2D67 B2D66 B2D65 B2D64 B2D63 B2D62 B2D61 B2D60 xxxx xxxx 57, 299
B2D5
(8)
B2D57 B2D56 B2D55 B2D54 B2D53 B2D52 B2D51 B2D50 xxxx xxxx 57, 299
B2D4
(8)
B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 57, 299
B2D3
(8)
B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 57, 299
B2D2
(8)
B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 57, 299
B2D1
(8)
B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D11 B2D10 xxxx xxxx 57, 299
B2D0
(8)
B2D07 B2D06 B2D05 B2D04 B2D03 B2D02 B2D01 B2D00 xxxx xxxx 57, 299
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X8X devices and are read as ‘0’. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X8X devices only.