Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 76 Preliminary © 2007 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 62
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 62
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 62
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 49, 63
PCLATU
— —bit 21
(1)
Holding Register for PC<20:16> ---0 0000 49, 62
PCLATH Holding Register for PC<15:8> 0000 0000 49, 62
PCL PC Low Byte (PC<7:0>) 0000 0000 49, 62
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 103
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 103
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 103
TABLAT Program Memory Table Latch 0000 0000 49, 103
PRODH Product Register High Byte xxxx xxxx 49, 111
PRODL Product Register Low Byte xxxx xxxx 49, 111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 115
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP1111 -1-1 49, 116
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 117
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 89
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 90
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 90
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 90
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register),
value of FSR0 offset by W
N/A 49, 90
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 49, 89
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 89
WREG Working Register xxxx xxxx 49
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 89
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 90
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 90
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 90
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register),
value of FSR1 offset by W
N/A 49, 90
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 49, 89
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 49, 89
BSR
— — — — Bank Select Register ---- 0000 50, 67
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 89
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 90
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 90
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 90
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register),
value of FSR2 offset by W
N/A 50, 90
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 50, 89
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50, 89
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X8X devices and are read as ‘0’. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X8X devices only.